From 4b6bf62bc0de1eaab9fb3c0c67121722e722aa3b Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Thu, 3 Sep 2020 21:32:56 -0700 Subject: [PATCH] update to match refactored power-instruction-analyzer API matches the api of power-instruction-analyzer commit e828d2acecc25a82d5c29b765163a10993547566 --- src/soc/fu/div/test/helper.py | 25 +++++++++++++------------ 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/src/soc/fu/div/test/helper.py b/src/soc/fu/div/test/helper.py index 3ca9ddfc..4c6bb5a7 100644 --- a/src/soc/fu/div/test/helper.py +++ b/src/soc/fu/div/test/helper.py @@ -74,7 +74,14 @@ def set_alu_inputs(alu, dec2, sim): yield from ALUHelpers.set_int_rb(alu, dec2, inp) yield from ALUHelpers.set_xer_so(alu, dec2, inp) - return pia.InstructionInput(ra=inp["ra"], rb=inp["rb"], rc=0) + + overflow = None + if 'xer_so' in inp: + so = inp['xer_so'] + overflow = pia.OverflowFlags(so=bool(so), + ov=False, + ov32=False) + return pia.InstructionInput(ra=inp["ra"], rb=inp["rb"], overflow=overflow) class DivTestHelper(unittest.TestCase): @@ -98,10 +105,7 @@ class DivTestHelper(unittest.TestCase): so = 1 if spr['XER'][XER_bits['SO']] else 0 ov = 1 if spr['XER'][XER_bits['OV']] else 0 ov32 = 1 if spr['XER'][XER_bits['OV32']] else 0 - xer_zero = not (so or ov or ov32) print("before: so/ov/32", so, ov, ov32) - else: - xer_zero = True # ask the decoder to decode this binary data (endian'd) # little / big? @@ -122,14 +126,11 @@ class DivTestHelper(unittest.TestCase): yield alu.p.valid_i.eq(0) opname = code.split(' ')[0] - if xer_zero: - fnname = opname.replace(".", "_") - print(f"{fnname}({pia_inputs})") - pia_res = getattr( - pia, opname.replace(".", "_"))(pia_inputs) - print(f"-> {pia_res}") - else: - pia_res = None + fnname = opname.replace(".", "_") + print(f"{fnname}({pia_inputs})") + pia_res = getattr( + pia, opname.replace(".", "_"))(pia_inputs) + print(f"-> {pia_res}") yield from isa_sim.call(opname) index = isa_sim.pc.CIA.value//4 -- 2.30.2