From 4b725d11e3eeff47f6958e3bbbfdc5b18bf46fe0 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 5 Feb 2020 17:38:08 +0000 Subject: [PATCH] quick test shows eq_gt_ge.py returning output in reverse order --- src/ieee754/part_cmp/eq_gt_ge.py | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/src/ieee754/part_cmp/eq_gt_ge.py b/src/ieee754/part_cmp/eq_gt_ge.py index 78a344b5..d010c21b 100644 --- a/src/ieee754/part_cmp/eq_gt_ge.py +++ b/src/ieee754/part_cmp/eq_gt_ge.py @@ -14,6 +14,7 @@ See: """ from nmigen import Signal, Module, Elaboratable, Cat, C, Mux, Repl +from nmigen.back.pysim import Simulator, Delay, Settle from nmigen.cli import main from ieee754.part_mul_add.partpoints import PartitionPoints @@ -91,3 +92,34 @@ class PartitionedEqGtGe(Elaboratable): comb += self.output.eq(gtc.outputs) return m + + def ports(self): + return [self.a, self.b, self.opcode, + self.partition_points.as_sig(), + self.output] + +if __name__ == "__main__": + from ieee754.part_mul_add.partpoints import make_partition + m = Module() + mask = Signal(4) + m.submodules.egg = egg = PartitionedEqGtGe(16, make_partition(mask, 16)) + + sim = Simulator(m) + + def process(): + yield mask.eq(0b10) + yield egg.a.eq(0xf000) + yield egg.b.eq(0) + yield Delay(1e-6) + out = yield egg.output + print ("out", bin(out)) + yield mask.eq(0b1111) + yield egg.a.eq(0x0000) + yield egg.b.eq(0) + yield Delay(1e-6) + out = yield egg.output + print ("out", bin(out)) + + sim.add_process(process) + with sim.write_vcd("eq_gt_ge.vcd", "eq_gt_ge.gtkw", traces=egg.ports()): + sim.run() -- 2.30.2