From 4b823aaa2741178408d34574a78e8b21981a7239 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 6 Dec 2021 17:14:45 +0000 Subject: [PATCH] start moving TLBArray into DTLBUpdate --- src/soc/experiment/dcache.py | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py index a32456c8..da5c6add 100644 --- a/src/soc/experiment/dcache.py +++ b/src/soc/experiment/dcache.py @@ -431,6 +431,7 @@ class Reservation(RecordObject): class DTLBUpdate(Elaboratable): def __init__(self): + self.dtlb = TLBArray() self.tlbie = Signal() self.tlbwe = Signal() self.doall = Signal() @@ -778,7 +779,8 @@ class DCache(Elaboratable): comb += tlbie.eq(r0_valid & r0.tlbie) comb += tlbwe.eq(r0_valid & r0.tlbld) - m.submodules.tlb_update = d = DTLBUpdate() + d = self.dtlb_update + with m.If(tlbie & r0.doall): # clear all valid bits at once for i in range(TLB_SET_SIZE): @@ -1603,7 +1605,6 @@ class DCache(Elaboratable): """note: these are passed to nmigen.hdl.Memory as "attributes". don't know how, just that they are. """ - dtlb = TLBArray() # TODO attribute ram_style of # dtlb_tags : signal is "distributed"; # TODO attribute ram_style of @@ -1682,6 +1683,10 @@ class DCache(Elaboratable): comb += self.bus.dat_w.eq(r1.wb.dat) comb += self.bus.cyc.eq(r1.wb.cyc) + # create submodule TLBUpdate + m.submodules.dtlb_update = self.dtlb_update = DTLBUpdate() + dtlb = self.dtlb_update.dtlb + # call sub-functions putting everything together, using shared # signals established above self.stage_0(m, r0, r1, r0_full) -- 2.30.2