From 4ba43903c4098a25add7f34513b876afea6f5491 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 10 Apr 2019 18:40:57 +0100 Subject: [PATCH] set is a python keyword, renamed to "cset" - short for "cache set" --- TLB/src/SetAssociativeCache.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/TLB/src/SetAssociativeCache.py b/TLB/src/SetAssociativeCache.py index 4e5a863a..37ad94d6 100644 --- a/TLB/src/SetAssociativeCache.py +++ b/TLB/src/SetAssociativeCache.py @@ -55,7 +55,7 @@ class SetAssociativeCache(): # Input self.enable = Signal(1) # Whether the cache is enabled self.command = Signal(2) # 00=None, 01=Read, 10=Write (see SA_XX) - self.set = Signal(max=set_count) # The set to be checked + self.cset = Signal(max=set_count) # The set to be checked self.tag = Signal(tag_size) # The tag to find self.data_i = Signal(data_size + tag_size) # The input data @@ -78,8 +78,8 @@ class SetAssociativeCache(): # value for i in range(self.way_count): m.d.comb += [ - self.write_port_array[i].addr.eq(self.set), - self.read_port_array[i].addr.eq(self.set) + self.write_port_array[i].addr.eq(self.cset), + self.read_port_array[i].addr.eq(self.cset) ] # Pull out active bit from data data = self.read_port_array[i].data; -- 2.30.2