From 4baa6af64380dc78acf3560c4fdfe1d991fa140e Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 3 Aug 2020 20:04:56 +0100
Subject: [PATCH] use new soc.config.state CoreState class in DMI and
 test_issuer

---
 src/soc/config/state.py  |  9 +++++++++
 src/soc/debug/dmi.py     | 11 +++++------
 src/soc/simple/issuer.py |  2 ++
 3 files changed, 16 insertions(+), 6 deletions(-)
 create mode 100644 src/soc/config/state.py

diff --git a/src/soc/config/state.py b/src/soc/config/state.py
new file mode 100644
index 00000000..4035543e
--- /dev/null
+++ b/src/soc/config/state.py
@@ -0,0 +1,9 @@
+from nmutil.iocontrol import RecordObject
+from nmigen import Signal
+
+
+class CoreState(RecordObject):
+    def __init__(self, name):
+        super().__init__(name=name)
+        self.pc = Signal(64)         # Program Counter (CIA, NIA)
+        self.msr = Signal(64)        # Machine Status Register (MSR)
diff --git a/src/soc/debug/dmi.py b/src/soc/debug/dmi.py
index 2a72786f..bff07d70 100644
--- a/src/soc/debug/dmi.py
+++ b/src/soc/debug/dmi.py
@@ -10,6 +10,7 @@ from nmigen import Elaboratable, Module, Signal, Cat, Const, Record, Array, Mux
 from nmutil.iocontrol import RecordObject
 from nmigen.utils import log2_int
 from nmigen.cli import rtlil
+from soc.config.state import CoreState
 
 
 # DMI register addresses
@@ -82,8 +83,7 @@ class CoreDebug(Elaboratable):
         # Core status inputs
         self.terminate_i    = Signal()
         self.core_stopped_i = Signal()
-        self.nia            = Signal(64)
-        self.msr            = Signal(64)
+        self.state = CoreState("core_dbg")
 
         # GSPR register read port
         self.dbg_gpr = DbgReg("dbg_gpr")
@@ -141,9 +141,9 @@ class CoreDebug(Elaboratable):
             with m.Case( DBGCore.STAT):
                 comb += self.dmi.dout.eq(stat_reg)
             with m.Case( DBGCore.NIA):
-                comb += self.dmi.dout.eq(self.nia)
+                comb += self.dmi.dout.eq(self.state.pc)
             with m.Case( DBGCore.MSR):
-                comb += self.dmi.dout.eq(self.msr)
+                comb += self.dmi.dout.eq(self.state.msr)
             with m.Case( DBGCore.GSPR_DATA):
                 comb += self.dmi.dout.eq(self.dbg_gpr.data_i)
             with m.Case( DBGCore.LOG_ADDR):
@@ -313,8 +313,7 @@ class CoreDebug(Elaboratable):
         yield self.icache_rst_o
         yield self.terminate_i
         yield self.core_stopped_i
-        yield self.nia
-        yield self.msr
+        yield from self.state
         yield from self.dbg_gpr
         yield self.log_data_i
         yield self.log_read_addr_i
diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index e625b8dd..c111f958 100644
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -119,6 +119,8 @@ class TestIssuer(Elaboratable):
         # TODO comb += core.reset_i.eq(dbg.core_rst_o)
         # TODO comb += core.icache_rst_i.eq(dbg.icache_rst_o)
         comb += dbg.terminate_i.eq(core.core_terminate_o)
+        comb += dbg.state.pc.eq(cur_pc)
+        comb += dbg.state.msr.eq(cur_msr)
 
         # temporaries
         core_busy_o = core.busy_o         # core is busy
-- 
2.30.2