From 4bbd03d76d2e03324f94ba23abcd20ab5e66feec Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 4 Dec 2019 22:02:30 -0800 Subject: [PATCH] kvm,arm: Update the KVM ARM v8 CPU to use vector regs. The exact mapping of the KVM registers and the gem5 registers is direct and may not actually be correct. Change-Id: Idb0981105c002e65755f8dfc315dbb95ea9370df Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23402 Reviewed-by: Giacomo Travaglini Maintainer: Giacomo Travaglini Tested-by: kokoro --- src/arch/arm/kvm/armv8_cpu.cc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/arch/arm/kvm/armv8_cpu.cc b/src/arch/arm/kvm/armv8_cpu.cc index 5a843fcd5..2ac97441d 100644 --- a/src/arch/arm/kvm/armv8_cpu.cc +++ b/src/arch/arm/kvm/armv8_cpu.cc @@ -249,10 +249,10 @@ ArmV8KvmCPU::updateKvmState() } for (int i = 0; i < NUM_QREGS; ++i) { - const RegIndex reg_base(i * FP_REGS_PER_VFP_REG); KvmFPReg reg; + auto v = tc->readVecReg(RegId(VecRegClass, i)).as(); for (int j = 0; j < FP_REGS_PER_VFP_REG; j++) - reg.s[j].i = tc->readFloatReg(reg_base + j); + reg.s[j].i = v[j]; setOneReg(kvmFPReg(i), reg.data); DPRINTF(KvmContext, " Q%i: %s\n", i, getAndFormatOneReg(kvmFPReg(i))); @@ -321,12 +321,12 @@ ArmV8KvmCPU::updateThreadContext() } for (int i = 0; i < NUM_QREGS; ++i) { - const RegIndex reg_base(i * FP_REGS_PER_VFP_REG); KvmFPReg reg; DPRINTF(KvmContext, " Q%i: %s\n", i, getAndFormatOneReg(kvmFPReg(i))); getOneReg(kvmFPReg(i), reg.data); + auto v = tc->getWritableVecReg(RegId(VecRegClass, i)).as(); for (int j = 0; j < FP_REGS_PER_VFP_REG; j++) - tc->setFloatReg(reg_base + j, reg.s[j].i); + v[j] = reg.s[j].i; } for (const auto &ri : getSysRegMap()) { -- 2.30.2