From 4bc5652a78786047aa55b8fcfbe200b658e58c30 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 1 Jun 2020 19:51:54 +0100 Subject: [PATCH] RS moved to port 1 (from port 3), remove need in ALU to read/mux into A operand --- libreriscv | 2 +- src/soc/fu/alu/test/test_pipe_caller.py | 7 +------ src/soc/fu/compunits/test/test_alu_compunit.py | 7 +------ src/soc/fu/compunits/test/test_logical_compunit.py | 7 +------ 4 files changed, 4 insertions(+), 19 deletions(-) diff --git a/libreriscv b/libreriscv index 177088bd..6a79599c 160000 --- a/libreriscv +++ b/libreriscv @@ -1 +1 @@ -Subproject commit 177088bdebe14a2e1173f8302127bbde504c3116 +Subproject commit 6a79599c792e9271203c29082ee512a46930be85 diff --git a/src/soc/fu/alu/test/test_pipe_caller.py b/src/soc/fu/alu/test/test_pipe_caller.py index 56a8770a..8517dc74 100644 --- a/src/soc/fu/alu/test/test_pipe_caller.py +++ b/src/soc/fu/alu/test/test_pipe_caller.py @@ -29,13 +29,8 @@ def set_alu_inputs(alu, dec2, sim): # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok)) # and place it into data_i.b - reg3_ok = yield dec2.e.read_reg3.ok reg1_ok = yield dec2.e.read_reg1.ok - assert reg3_ok != reg1_ok - if reg3_ok: - data1 = yield dec2.e.read_reg3.data - data1 = sim.gpr(data1).value - elif reg1_ok: + if reg1_ok: data1 = yield dec2.e.read_reg1.data data1 = sim.gpr(data1).value else: diff --git a/src/soc/fu/compunits/test/test_alu_compunit.py b/src/soc/fu/compunits/test/test_alu_compunit.py index 840bda32..0c7b0623 100644 --- a/src/soc/fu/compunits/test/test_alu_compunit.py +++ b/src/soc/fu/compunits/test/test_alu_compunit.py @@ -20,13 +20,8 @@ class ALUTestRunner(TestRunner): res = {} # RA (or RC) - reg3_ok = yield dec2.e.read_reg3.ok reg1_ok = yield dec2.e.read_reg1.ok - assert reg3_ok != reg1_ok - if reg3_ok: - data1 = yield dec2.e.read_reg3.data - res['a'] = sim.gpr(data1).value - elif reg1_ok: + if reg1_ok: data1 = yield dec2.e.read_reg1.data res['a'] = sim.gpr(data1).value diff --git a/src/soc/fu/compunits/test/test_logical_compunit.py b/src/soc/fu/compunits/test/test_logical_compunit.py index 1c9258b8..0ba7e8d9 100644 --- a/src/soc/fu/compunits/test/test_logical_compunit.py +++ b/src/soc/fu/compunits/test/test_logical_compunit.py @@ -20,13 +20,8 @@ class LogicalTestRunner(TestRunner): res = {} # RA (or RC) - reg3_ok = yield dec2.e.read_reg3.ok reg1_ok = yield dec2.e.read_reg1.ok - assert reg3_ok != reg1_ok - if reg3_ok: - data1 = yield dec2.e.read_reg3.data - res['a'] = sim.gpr(data1).value - elif reg1_ok: + if reg1_ok: data1 = yield dec2.e.read_reg1.data res['a'] = sim.gpr(data1).value -- 2.30.2