From 4bc97d3d227ec5753585ba5f50188918931ed40b Mon Sep 17 00:00:00 2001 From: IkiWiki Date: Sun, 18 Sep 2022 16:36:39 +0100 Subject: [PATCH] dummy commit --- openpower/sv/rfc/ls001.mdwn | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn index d9ebd84a7..c8722ac68 100644 --- a/openpower/sv/rfc/ls001.mdwn +++ b/openpower/sv/rfc/ls001.mdwn @@ -345,7 +345,8 @@ mask `sv.bc/pm=r3`. Traditional Vector ISAs have vastly more (and more complex) addressing modes: unit strided, element strided, Indexed, Structure Packing. All of these had to be jammed in on top of existing Scalar instructions -**without modifying the Scalar instructions**. A small conceptual +**without modifying or adding new Scalar instructions**. +A small conceptual "cheat" was therefore needed. The Immediate (D) is in some Modes multiplied by the element index, which gives us element-strided. For unit-strided the width of the operation (`ld`, 8 byte) is -- 2.30.2