From 4bd8879b04dcb9c4c0ae062ea7e4ebc2b9c95fe0 Mon Sep 17 00:00:00 2001 From: Cole Poirier Date: Sat, 15 Aug 2020 16:17:14 -0700 Subject: [PATCH] mmu.py fixes https://bugs.libre-soc.org/show_bug.cgi?id=450#c53 --- src/soc/experiment/mmu.py | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/soc/experiment/mmu.py b/src/soc/experiment/mmu.py index d68a9fae..df9af18c 100644 --- a/src/soc/experiment/mmu.py +++ b/src/soc/experiment/mmu.py @@ -1001,21 +1001,25 @@ class MMU1(Elaboratable): # addr := r.addr; # tlb_data := (others => '0'); comb += addr.eq(r.addr) + comb += tlb_data.eq(0) # elsif tlb_load = '1' then with m.If(tlb_load): # addr := r.addr(63 downto 12) & x"000"; # tlb_data := pte; comb += addr.eq(Cat(Const(0x000, 12), r.addr[12:64])) + comb += tlb_data.eq(pte) # elsif prtbl_rd = '1' then with m.If(prtbl_rd): # addr := prtable_addr; # tlb_data := (others => '0'); comb += addr.eq(prtable_addr) + comb += tlb_data.eq(0) # else with m.Else(): # addr := pgtable_addr; # tlb_data := (others => '0'); comb += addr.eq(pgtable_addr) + comb += tlb_data.eq(0) # end if; # l_out.done <= r.done; -- 2.30.2