From 4bdd272e73b893784eaea9811d8c9e80a7b25ceb Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 15 Sep 2020 10:13:43 +0100 Subject: [PATCH] add mmu initial pipe_data.py --- src/soc/fu/mmu/__init__.py | 0 src/soc/fu/mmu/pipe_data.py | 41 +++++++++++++++++++++++++++++++++++++ 2 files changed, 41 insertions(+) create mode 100644 src/soc/fu/mmu/__init__.py create mode 100644 src/soc/fu/mmu/pipe_data.py diff --git a/src/soc/fu/mmu/__init__.py b/src/soc/fu/mmu/__init__.py new file mode 100644 index 00000000..e69de29b diff --git a/src/soc/fu/mmu/pipe_data.py b/src/soc/fu/mmu/pipe_data.py new file mode 100644 index 00000000..5affde65 --- /dev/null +++ b/src/soc/fu/mmu/pipe_data.py @@ -0,0 +1,41 @@ +"""MMU Pipeline Data structures + +Covers MFMMU and MTMMU for MMU MMUs (dsisr, dar), and DCBZ and TLBIE. + +Note: RB is *redirected* (in the decoder CSV files) to the field that +happens, here, to be named "ra"! yes wonderfully confusing. similar +thing goes on with shift_rot. + +Links: +* https://bugs.libre-soc.org/show_bug.cgi?id=491 +* https://libre-soc.org/3d_gpu/architecture/regfile/ +""" + +from soc.fu.pipe_data import IntegerData +from soc.fu.mmu.mmu_input_record import CompMMUOpSubset +from soc.fu.alu.pipe_data import CommonPipeSpec + + +class MMUInputData(IntegerData): + regspec = [('INT', 'ra', '0:63'), # RA + ('SPR', 'spr1', '0:63'), # MMU (slow) + ('FAST', 'fast1', '0:63'), # MMU (fast: LR, CTR etc) + ] + def __init__(self, pspec): + super().__init__(pspec, False) + # convenience + self.a = self.ra + + +class MMUOutputData(IntegerData): + regspec = [('INT', 'o', '0:63'), # RT + ('SPR', 'spr1', '0:63'), # MMU (slow) + ('FAST', 'fast1', '0:63'), # MMU (fast: LR, CTR etc) + ] + def __init__(self, pspec): + super().__init__(pspec, True) + + +class MMUPipeSpec(CommonPipeSpec): + regspec = (MMUInputData.regspec, MMUOutputData.regspec) + opsubsetkls = CompMMUOpSubset -- 2.30.2