From 4c0eb14bc8553d6e97f1cf70276c6a4fa67b7c38 Mon Sep 17 00:00:00 2001 From: Tom de Vries Date: Wed, 30 Sep 2020 11:51:41 +0200 Subject: [PATCH] [testsuite] Re-enable pr94600-{1,3}.c tests for arm Before commit 7e437162001 "[testsuite] Require non_strict_align in pr94600-{1,3}.c", some tests were failing for nvptx, because volatile stores were expected, but memcpy's were found instead. This was traced back to this bit in compute_record_mode: ... /* If structure's known alignment is less than what the scalar mode would need, and it matters, then stick with BLKmode. */ if (mode != BLKmode && STRICT_ALIGNMENT && ! (TYPE_ALIGN (type) >= BIGGEST_ALIGNMENT || TYPE_ALIGN (type) >= GET_MODE_ALIGNMENT (mode))) { /* If this is the only reason this type is BLKmode, then don't force containing types to be BLKmode. */ TYPE_NO_FORCE_BLK (type) = 1; mode = BLKmode; } ... which got triggered for nvptx, but not for x86_64. The commit disabled the tests for non_strict_align effective target, but that had the effect for the arm target that those tests were disabled, even though they were passing before. Further investigation in compute_record_mode shows that the if-condition evaluates to false for arm because, because TYPE_ALIGN (type) == 32, while it's 8 for nvptx. This again can be explained by the PCC_BITFIELD_TYPE_MATTERS setting, which is 1 for arm, but 0 for nvptx. Re-enable the test for arm by using effective target (non_strict_align || pcc_bitfield_type_matters). Tested on arm-eabi and nvptx. gcc/testsuite/ChangeLog: 2020-09-30 Tom de Vries * gcc.dg/pr94600-1.c: Use effective target (non_strict_align || pcc_bitfield_type_matters). * gcc.dg/pr94600-3.c: Same. --- gcc/testsuite/gcc.dg/pr94600-1.c | 4 ++-- gcc/testsuite/gcc.dg/pr94600-3.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/gcc/testsuite/gcc.dg/pr94600-1.c b/gcc/testsuite/gcc.dg/pr94600-1.c index 38f939a98cb..c9a7bb9007e 100644 --- a/gcc/testsuite/gcc.dg/pr94600-1.c +++ b/gcc/testsuite/gcc.dg/pr94600-1.c @@ -32,5 +32,5 @@ foo(void) } /* The only volatile accesses should be the obvious writes. */ -/* { dg-final { scan-rtl-dump-times {\(mem/v} 6 "final" { target { non_strict_align } } } } */ -/* { dg-final { scan-rtl-dump-times {\(set \(mem/v} 6 "final" { target { non_strict_align } } } } */ +/* { dg-final { scan-rtl-dump-times {\(mem/v} 6 "final" { target { non_strict_align || pcc_bitfield_type_matters } } } } */ +/* { dg-final { scan-rtl-dump-times {\(set \(mem/v} 6 "final" { target { non_strict_align || pcc_bitfield_type_matters } } } } */ diff --git a/gcc/testsuite/gcc.dg/pr94600-3.c b/gcc/testsuite/gcc.dg/pr94600-3.c index e8776fbdb28..ff42c7db3c6 100644 --- a/gcc/testsuite/gcc.dg/pr94600-3.c +++ b/gcc/testsuite/gcc.dg/pr94600-3.c @@ -31,5 +31,5 @@ foo(void) } /* The loop isn't unrolled. */ -/* { dg-final { scan-rtl-dump-times {\(mem/v} 1 "final" { target { non_strict_align } } } } */ -/* { dg-final { scan-rtl-dump-times {\(set \(mem/v} 1 "final" { target { non_strict_align } } } } */ +/* { dg-final { scan-rtl-dump-times {\(mem/v} 1 "final" { target { non_strict_align || pcc_bitfield_type_matters } } } } */ +/* { dg-final { scan-rtl-dump-times {\(set \(mem/v} 1 "final" { target { non_strict_align || pcc_bitfield_type_matters } } } } */ -- 2.30.2