From 4c37e781a17b3638897f14eba6ef7bab9e619568 Mon Sep 17 00:00:00 2001 From: lkcl Date: Wed, 30 Dec 2020 21:57:25 +0000 Subject: [PATCH] --- openpower/sv/svp64.mdwn | 24 +++++++++++++++--------- 1 file changed, 15 insertions(+), 9 deletions(-) diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn index 9abaed8a6..dbcd1b747 100644 --- a/openpower/sv/svp64.mdwn +++ b/openpower/sv/svp64.mdwn @@ -159,7 +159,7 @@ The following fields are common to all Remapped Encodings: | Field Name | Field bits | Description | |------------|------------|----------------------------------------| -| MASK\_KIND | `0` | Execution (predication) Mask Kind | +| MASKMODE | `0` | Execution (predication) Mask Kind | | MASK | `1:3` | Execution Mask | | ELWIDTH | `4:5` | Element Width | | ELWIDTH_SRC | `6:7` | Element Width for Source | @@ -169,7 +169,7 @@ The following fields are common to all Remapped Encodings: * MODE changes the behaviour of the SV operation (result saturation, mapreduce) * SUBVL groups elements together into vec2, vec3, vec4 for use in 3D and Audio/Video DSP work * ELWIDTH and ELWIDTH_SRC overrides the instruction's destination and source operand width -* MASK and MASK_KIND provide predication (two types of sources: scalar INT and Vector CR). +* MASK (and MASK_SRC) and MASKMODE provide predication (two types of sources: scalar INT and Vector CR). Bits 10 to 18 are further decoded depending on RM category for the instruction. Similar to OpenPOWER `X-Form` etc. these are given designations, such as `RM-1P-3S1D` which indicates for this example that the operation is to be single-predicated and that there are 3 source operand EXTRA tags and one destination operand tag. @@ -287,21 +287,23 @@ The SUBVL encoding value may be thought of as an inclusive range of a sub-vector. SUBVL=2 represents a vec2, its encoding is 0b01, therefore this may be considered to be elements 0b00 to 0b01 inclusive. -# MASK/MASK_SRC & MASK_KIND Encoding +# MASK/MASK_SRC & MASKMODE Encoding TODO: rename MASK_KIND to MASKMODE One bit (`MASKMODE`) indicates the mode: CR or Int predication. The two types may not be mixed. -Special note: to get default behaviour (SV disabled) this field must +Special note: to disable predication this field must be set to zero in combination with Integer Predication also being set to 0b000. this has the effect of enabling "all 1s" in the predicate mask, which is equivalent to "not having any predication at all" and consequently, in combination with all other default zeros, fully -disables SV. +disables SV (`scalar identity behaviour`). -| MASK\_KIND Value | Description | +`MASKMODE` may be set to one of 2 values: + +| Value | Description | |-----------|------------------------------------------------------| | 0 | MASK/MASK_SRC are encoded using Integer Predication | | 1 | MASK/MASK_SRC are encoded using CR-based Predication | @@ -313,11 +315,13 @@ for both src and dest, or different regs (one for src, one for dest). Likewise CR based twin predication has a second set of 3 bits, allowing a different test to be applied. -## Integer Predication (MASK_KIND=0) +## Integer Predication (MASKMODE=0) When the predicate mode bit is zero the 3 bits are interpreted as below. Twin predication has an identical 3 bit field similarly encoded. +`MASK` and `MASK_SRC` may be set to one of 8 values, to provide the following meaning: + | Value | Mnemonic | Element `i` enabled if: | |-------|----------|------------------------------| | 000 | ALWAYS | predicate effectively all 1s | @@ -329,10 +333,12 @@ Twin predication has an identical 3 bit field similarly encoded. | 110 | R30 | `R30 & (1 << i)` is non-zero | | 111 | ~R30 | `R30 & (1 << i)` is zero | -## CR-based Predication (MASK_KIND=1) +## CR-based Predication (MASKMODE=1) When the predicate mode bit is one the 3 bits are interpreted as below. -Twin predication has an identical 3 bit field similarly encoded +Twin predication has an identical 3 bit field similarly encoded. + +`MASK` and `MASK_SRC` may be set to one of 8 values, to provide the following meaning: | Value | Mnemonic | Element `i` is enabled if | |-------|----------|--------------------------| -- 2.30.2