From 4c43e165603fd21e05a1d3eb5d5e78fde38f10e9 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 1 Oct 2022 22:40:21 +0100 Subject: [PATCH] replacing setvl-svstep with just svstep --- src/openpower/decoder/isa/test_caller_svstate.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/openpower/decoder/isa/test_caller_svstate.py b/src/openpower/decoder/isa/test_caller_svstate.py index 7612b5c6..bfc7a5b6 100644 --- a/src/openpower/decoder/isa/test_caller_svstate.py +++ b/src/openpower/decoder/isa/test_caller_svstate.py @@ -68,10 +68,10 @@ class SVSTATETestCase(FHDLTestCase): lst = SVP64Asm(["setvl 0, 0, 2, 1, 1, 1", 'sv.add 1, *5, *9', 'sv.addi *12, 1, 1', - "setvl. 0, 0, 1, 1, 0, 0", + "svstep. 0, 1, 0", 'sv.add 1, *5, *9', 'sv.addi *12, 1, 1', - "setvl. 0, 0, 1, 1, 0, 0" + "svstep. 0, 1, 0", ]) sequence is as follows: @@ -100,10 +100,10 @@ class SVSTATETestCase(FHDLTestCase): lst = SVP64Asm(["setvl 0, 0, 2, 1, 1, 1", 'sv.add 1, *5, *9', # scalar dest (into r1) 'sv.addi *12, 1, 1', # scalar src (from r1) - "setvl. 0, 0, 1, 1, 0, 0", # svstep + "svstep. 0, 1, 0", # svstep 'sv.add 1, *5, *9', # again, scalar dest 'sv.addi *12, 1, 1', # but vector dest - "setvl. 0, 0, 1, 1, 0, 0" # svstep (end: sets CR0.SO) + "svstep. 0, 1, 0", # svstep (end: sets CR0.SO) ]) lst = list(lst) -- 2.30.2