From 4c5e00eccf134169e62ca2b1d0f314e45dd8d71f Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 23 Sep 2022 22:42:49 +0100 Subject: [PATCH] whoops consistent inversion of inv,CRbit was CRbit,inv --- src/openpower/decoder/power_insn.py | 2 +- src/openpower/sv/trans/svp64.py | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/openpower/decoder/power_insn.py b/src/openpower/decoder/power_insn.py index c4152057..75879f86 100644 --- a/src/openpower/decoder/power_insn.py +++ b/src/openpower/decoder/power_insn.py @@ -1305,7 +1305,7 @@ class FFPRRc1BaseRM(BaseRM): def specifiers(self, record, mode): inv = _SelectableInt(value=int(self.inv), bits=1) CR = _SelectableInt(value=int(self.CR), bits=2) - mask = int(_selectconcat(inv, CR)) + mask = int(_selectconcat(CR, inv)) predicate = PredicateBaseRM.predicate(True, mask) yield f"{mode}={predicate}" diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py index a3e6f44b..eb1f8115 100644 --- a/src/openpower/sv/trans/svp64.py +++ b/src/openpower/sv/trans/svp64.py @@ -669,8 +669,8 @@ def decode_bo(encoding): # barse-ackwards MSB0/LSB0. sigh mapped = pmap[encoding] si = SelectableInt(0, 3) - si[0] = mapped>>2 # inv - si[1:3] = mapped & 3 # CR + si[0] = mapped & 1 # inv + si[1:3] = mapped >> 1 # CR return int(si) -- 2.30.2