From 4c7a7796ade354a41fac9b4c14d4715cbe9e78c4 Mon Sep 17 00:00:00 2001
From: Ali Saidi <Ali.Saidi@ARM.com>
Date: Thu, 17 Mar 2011 19:20:20 -0500
Subject: [PATCH] ARM: Implement the Instruction Set Attribute Registers
 (ISAR).

The ISAR registers describe which features the processor supports.
Transcribe the values listed in section B5.2.5 of the ARM ARM
into the registers as read-only values
---
 src/arch/arm/isa.cc      | 10 ++++++++++
 src/arch/arm/miscregs.hh | 17 ++++++++---------
 2 files changed, 18 insertions(+), 9 deletions(-)

diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 4bdbe77ce..d720becba 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -143,6 +143,16 @@ ISA::clear()
 
     miscRegs[MISCREG_CPACR] = 0;
     miscRegs[MISCREG_FPSID] = 0x410430A0;
+
+    // See section B4.1.84 of ARM ARM
+    // All values are latest for ARMv7-A profile
+    miscRegs[MISCREG_ID_ISAR0] = 0x01101111;
+    miscRegs[MISCREG_ID_ISAR1] = 0x02112111;
+    miscRegs[MISCREG_ID_ISAR2] = 0x21232141;
+    miscRegs[MISCREG_ID_ISAR3] = 0x01112131;
+    miscRegs[MISCREG_ID_ISAR4] = 0x10010142;
+    miscRegs[MISCREG_ID_ISAR5] = 0x00000000;
+
     //XXX We need to initialize the rest of the state.
 }
 
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index 90b4fd999..47495a4e7 100644
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -165,6 +165,12 @@ namespace ArmISA
         MISCREG_PMUSERENR,
         MISCREG_PMINTENSET,
         MISCREG_PMINTENCLR,
+        MISCREG_ID_ISAR0,
+        MISCREG_ID_ISAR1,
+        MISCREG_ID_ISAR2,
+        MISCREG_ID_ISAR3,
+        MISCREG_ID_ISAR4,
+        MISCREG_ID_ISAR5,
         MISCREG_CP15_UNIMP_START,
         MISCREG_TCMTR = MISCREG_CP15_UNIMP_START,
         MISCREG_ID_PFR1,
@@ -173,12 +179,6 @@ namespace ArmISA
         MISCREG_ID_MMFR1,
         MISCREG_ID_MMFR2,
         MISCREG_ID_MMFR3,
-        MISCREG_ID_ISAR0,
-        MISCREG_ID_ISAR1,
-        MISCREG_ID_ISAR2,
-        MISCREG_ID_ISAR3,
-        MISCREG_ID_ISAR4,
-        MISCREG_ID_ISAR5,
         MISCREG_AIDR,
         MISCREG_ADFSR,
         MISCREG_AIFSR,
@@ -233,13 +233,12 @@ namespace ArmISA
         "pmswinc", "pmselr", "pmceid0",
         "pmceid1", "pmc_other", "pmxevcntr",
         "pmuserenr", "pmintenset", "pmintenclr",
+        "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
          // Unimplemented below
         "tcmtr",
         "id_pfr1", "id_dfr0", "id_afr0",
         "id_mmfr1", "id_mmfr2", "id_mmfr3",
-        "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
-        "aidr",
-        "adfsr", "aifsr",
+        "aidr", "adfsr", "aifsr",
         "dcimvac", "dcisw", "mccsw",
         "dccmvau",
         "nsacr",
-- 
2.30.2