From 4c80b12b1a96fee64bfbdd35d097d867599eee1e Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Tue, 21 Mar 2017 16:40:01 -0700 Subject: [PATCH] riscv: remove dependency on num_cores --- riscv/encoding.h | 3 --- riscv/interactive.cc | 2 +- riscv/processor.cc | 1 - 3 files changed, 1 insertion(+), 5 deletions(-) diff --git a/riscv/encoding.h b/riscv/encoding.h index 60ee674..ef68c2f 100644 --- a/riscv/encoding.h +++ b/riscv/encoding.h @@ -137,9 +137,6 @@ #define IRQ_HOST 13 #define DEFAULT_RSTVEC 0x00001000 -#define DEFAULT_NMIVEC 0x00001004 -#define DEFAULT_MTVEC 0x00001010 -#define CONFIG_STRING_ADDR 0x0000100C #define EXT_IO_BASE 0x40000000 #define DRAM_BASE 0x80000000 diff --git a/riscv/interactive.cc b/riscv/interactive.cc index 623c425..ee88375 100644 --- a/riscv/interactive.cc +++ b/riscv/interactive.cc @@ -24,7 +24,7 @@ processor_t *sim_t::get_core(const std::string& i) { char *ptr; unsigned long p = strtoul(i.c_str(), &ptr, 10); - if (*ptr || p >= num_cores()) + if (*ptr || p >= procs.size()) throw trap_interactive(); return get_core(p); } diff --git a/riscv/processor.cc b/riscv/processor.cc index aa69bdc..f6b4cb6 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -118,7 +118,6 @@ void state_t::reset() memset(this, 0, sizeof(*this)); prv = PRV_M; pc = DEFAULT_RSTVEC; - mtvec = DEFAULT_MTVEC; load_reservation = -1; tselect = 0; for (unsigned int i = 0; i < num_triggers; i++) -- 2.30.2