From 4c82e53713b002cb056a0ae95cf9de9b60f098bc Mon Sep 17 00:00:00 2001 From: Tobias Platen Date: Thu, 24 Mar 2022 16:47:11 +0100 Subject: [PATCH] try using plru_dummy.vhdl --- Makefile | 4 ++-- plru_dummy.vhdl | 27 +++++++++++++++++++++++++++ 2 files changed, 29 insertions(+), 2 deletions(-) create mode 100644 plru_dummy.vhdl diff --git a/Makefile b/Makefile index 77c453f..73057f2 100644 --- a/Makefile +++ b/Makefile @@ -234,7 +234,7 @@ _fpga_files = fpga/soc_reset.vhdl \ _soc_files = wishbone_arbiter.vhdl wishbone_bram_wrapper.vhdl sync_fifo.vhdl \ wishbone_debug_master.vhdl xics.vhdl syscon.vhdl soc.vhdl \ - spi_rxtx.vhdl spi_flash_ctrl.vhdl + spi_rxtx.vhdl spi_flash_ctrl.vhdl plru_dummy.vhdl #-- @@ -250,7 +250,7 @@ ifeq ($(EXTERNAL_CORE),false) else #incomplete: does not build yet util_files = decode_types.vhdl common.vhdl wishbone_types.vhdl utils.vhdl \ - core_dummy.vhdl helpers.vhdl gpio.vhdl cache_ram.vhdl plru.vhdl + core_dummy.vhdl helpers.vhdl gpio.vhdl cache_ram.vhdl fpga_files = $(_fpga_files) $(_soc_files) synth_files = $(util_files) $(soc_extra_synth) $(fpga_files) $(clkgen) $(toplevel) $(dmi_dtm) soc_extra_v = external_core_top.v diff --git a/plru_dummy.vhdl b/plru_dummy.vhdl new file mode 100644 index 0000000..cdd989e --- /dev/null +++ b/plru_dummy.vhdl @@ -0,0 +1,27 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.all; + +entity plru is + generic ( + BITS : positive := 2 + ) + ; + port ( + clk : in std_ulogic; + rst : in std_ulogic; + + acc : in std_ulogic_vector(BITS-1 downto 0); + acc_en : in std_ulogic; + lru : out std_ulogic_vector(BITS-1 downto 0) + ); +end entity plru; + +architecture rtl of plru is + +begin + +end; + + -- 2.30.2