From 4c8efdbef45d98109769cf675ee3411393e8ed06 Mon Sep 17 00:00:00 2001 From: "Bobby R. Bruce" Date: Sun, 1 Dec 2019 12:36:32 -0800 Subject: [PATCH] tests: Migrated insttest tests to be run via `./main.py run` Some of these tests are ignored due to them failing. These should be fixed at a later date. Change-Id: Ida2810e00b7c9daa6b33caa01ab9dfd5b79bf03e Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24323 Reviewed-by: Hoa Nguyen Maintainer: Bobby R. Bruce Tested-by: kokoro --- tests/gem5/.testignore | 99 ++++++++ .../ref/riscv/linux/insttest-rv64a/simout | 41 ++++ .../ref/riscv/linux/insttest-rv64c/simout | 60 +++++ .../ref/riscv/linux/insttest-rv64d/simout | 218 ++++++++++++++++++ .../ref/riscv/linux/insttest-rv64f/simout | 214 +++++++++++++++++ .../ref/riscv/linux/insttest-rv64i/simout | 164 +++++++++++++ .../ref/riscv/linux/insttest-rv64m/simout | 43 ++++ tests/gem5/insttest_se/ref/sparc/linux/simout | 23 ++ tests/gem5/insttest_se/test.py | 78 +++++++ 9 files changed, 940 insertions(+) create mode 100644 tests/gem5/insttest_se/ref/riscv/linux/insttest-rv64a/simout create mode 100644 tests/gem5/insttest_se/ref/riscv/linux/insttest-rv64c/simout create mode 100644 tests/gem5/insttest_se/ref/riscv/linux/insttest-rv64d/simout create mode 100644 tests/gem5/insttest_se/ref/riscv/linux/insttest-rv64f/simout create mode 100644 tests/gem5/insttest_se/ref/riscv/linux/insttest-rv64i/simout create mode 100644 tests/gem5/insttest_se/ref/riscv/linux/insttest-rv64m/simout create mode 100755 tests/gem5/insttest_se/ref/sparc/linux/simout create mode 100644 tests/gem5/insttest_se/test.py diff --git a/tests/gem5/.testignore b/tests/gem5/.testignore index bca395dde..1c0c1bf30 100644 --- a/tests/gem5/.testignore +++ b/tests/gem5/.testignore @@ -34,3 +34,102 @@ test-hello-ALPHA-i386-fast test-hello-ALPHA-aarch64-opt test-hello-ALPHA-aarch64-debug test-hello-ALPHA-aarch64-fast +test-insttest-rv64a-linux-MinorCPU-RISCV-x86_64-opt +test-insttest-rv64c-linux-MinorCPU-RISCV-x86_64-opt +test-insttest-rv64d-linux-MinorCPU-RISCV-x86_64-opt +test-insttest-rv64f-linux-MinorCPU-RISCV-x86_64-opt +test-insttest-rv64i-linux-MinorCPU-RISCV-x86_64-opt +test-insttest-rv64m-linux-MinorCPU-RISCV-x86_64-opt +test-insttest-rv64i-linux-AtomicSimpleCPU-RISCV-x86_64-opt +test-insttest-rv64i-linux-TimingSimpleCPU-RISCV-x86_64-opt +test-insttest-rv64i-linux-DerivO3CPU-RISCV-x86_64-opt +test-insttest-linux-AtomicSimpleCPU-SPARC-x86_64-opt +test-insttest-linux-TimingSimpleCPU-SPARC-x86_64-opt +test-insttest-rv64a-linux-MinorCPU-RISCV-x86_64-debug +test-insttest-rv64c-linux-MinorCPU-RISCV-x86_64-debug +test-insttest-rv64d-linux-MinorCPU-RISCV-x86_64-debug +test-insttest-rv64f-linux-MinorCPU-RISCV-x86_64-debug +test-insttest-rv64i-linux-MinorCPU-RISCV-x86_64-debug +test-insttest-rv64m-linux-MinorCPU-RISCV-x86_64-debug +test-insttest-rv64i-linux-AtomicSimpleCPU-RISCV-x86_64-debug +test-insttest-rv64i-linux-TimingSimpleCPU-RISCV-x86_64-debug +test-insttest-rv64i-linux-DerivO3CPU-RISCV-x86_64-debug +test-insttest-linux-AtomicSimpleCPU-SPARC-x86_64-debug +test-insttest-linux-TimingSimpleCPU-SPARC-x86_64-debug +test-insttest-rv64a-linux-MinorCPU-RISCV-x86_64-fast +test-insttest-rv64c-linux-MinorCPU-RISCV-x86_64-fast +test-insttest-rv64d-linux-MinorCPU-RISCV-x86_64-fast +test-insttest-rv64f-linux-MinorCPU-RISCV-x86_64-fast +test-insttest-rv64i-linux-MinorCPU-RISCV-x86_64-fast +test-insttest-rv64m-linux-MinorCPU-RISCV-x86_64-fast +test-insttest-rv64i-linux-AtomicSimpleCPU-RISCV-x86_64-fast +test-insttest-rv64i-linux-TimingSimpleCPU-RISCV-x86_64-fast +test-insttest-rv64i-linux-DerivO3CPU-RISCV-x86_64-fast +test-insttest-linux-AtomicSimpleCPU-SPARC-x86_64-fast +test-insttest-linux-TimingSimpleCPU-SPARC-x86_64-fast +test-insttest-rv64a-linux-MinorCPU-RISCV-arch64-opt +test-insttest-rv64c-linux-MinorCPU-RISCV-arch64-opt +test-insttest-rv64d-linux-MinorCPU-RISCV-arch64-opt +test-insttest-rv64f-linux-MinorCPU-RISCV-arch64-opt +test-insttest-rv64i-linux-MinorCPU-RISCV-arch64-opt +test-insttest-rv64m-linux-MinorCPU-RISCV-arch64-opt +test-insttest-rv64i-linux-AtomicSimpleCPU-RISCV-arch64-opt +test-insttest-rv64i-linux-TimingSimpleCPU-RISCV-arch64-opt +test-insttest-rv64i-linux-DerivO3CPU-RISCV-arch64-opt +test-insttest-linux-AtomicSimpleCPU-SPARC-arch64-opt +test-insttest-linux-TimingSimpleCPU-SPARC-arch64-opt +test-insttest-rv64a-linux-MinorCPU-RISCV-arch64-debug +test-insttest-rv64c-linux-MinorCPU-RISCV-arch64-debug +test-insttest-rv64d-linux-MinorCPU-RISCV-arch64-debug +test-insttest-rv64f-linux-MinorCPU-RISCV-arch64-debug +test-insttest-rv64i-linux-MinorCPU-RISCV-arch64-debug +test-insttest-rv64m-linux-MinorCPU-RISCV-arch64-debug +test-insttest-rv64i-linux-AtomicSimpleCPU-RISCV-arch64-debug +test-insttest-rv64i-linux-TimingSimpleCPU-RISCV-arch64-debug +test-insttest-rv64i-linux-DerivO3CPU-RISCV-arch64-debug +test-insttest-linux-AtomicSimpleCPU-SPARC-arch64-debug +test-insttest-linux-TimingSimpleCPU-SPARC-arch64-debug +test-insttest-rv64a-linux-MinorCPU-RISCV-arch64-fast +test-insttest-rv64c-linux-MinorCPU-RISCV-arch64-fast +test-insttest-rv64d-linux-MinorCPU-RISCV-arch64-fast +test-insttest-rv64f-linux-MinorCPU-RISCV-arch64-fast +test-insttest-rv64i-linux-MinorCPU-RISCV-arch64-fast +test-insttest-rv64m-linux-MinorCPU-RISCV-arch64-fast +test-insttest-rv64i-linux-AtomicSimpleCPU-RISCV-arch64-fast +test-insttest-rv64i-linux-TimingSimpleCPU-RISCV-arch64-fast +test-insttest-rv64i-linux-DerivO3CPU-RISCV-arch64-fast +test-insttest-linux-AtomicSimpleCPU-SPARC-arch64-fast +test-insttest-linux-TimingSimpleCPU-SPARC-arch64-fast +test-insttest-rv64a-linux-MinorCPU-RISCV-i386-opt +test-insttest-rv64c-linux-MinorCPU-RISCV-i386-opt +test-insttest-rv64d-linux-MinorCPU-RISCV-i386-opt +test-insttest-rv64f-linux-MinorCPU-RISCV-i386-opt +test-insttest-rv64i-linux-MinorCPU-RISCV-i386-opt +test-insttest-rv64m-linux-MinorCPU-RISCV-i386-opt +test-insttest-rv64i-linux-AtomicSimpleCPU-RISCV-i386-opt +test-insttest-rv64i-linux-TimingSimpleCPU-RISCV-i386-opt +test-insttest-rv64i-linux-DerivO3CPU-RISCV-i386-opt +test-insttest-linux-AtomicSimpleCPU-SPARC-i386-opt +test-insttest-linux-TimingSimpleCPU-SPARC-i386-opt +test-insttest-rv64a-linux-MinorCPU-RISCV-i386-debug +test-insttest-rv64c-linux-MinorCPU-RISCV-i386-debug +test-insttest-rv64d-linux-MinorCPU-RISCV-i386-debug +test-insttest-rv64f-linux-MinorCPU-RISCV-i386-debug +test-insttest-rv64i-linux-MinorCPU-RISCV-i386-debug +test-insttest-rv64m-linux-MinorCPU-RISCV-i386-debug +test-insttest-rv64i-linux-AtomicSimpleCPU-RISCV-i386-debug +test-insttest-rv64i-linux-TimingSimpleCPU-RISCV-i386-debug +test-insttest-rv64i-linux-DerivO3CPU-RISCV-i386-debug +test-insttest-linux-AtomicSimpleCPU-SPARC-i386-debug +test-insttest-linux-TimingSimpleCPU-SPARC-i386-debug +test-insttest-rv64a-linux-MinorCPU-RISCV-i386-fast +test-insttest-rv64c-linux-MinorCPU-RISCV-i386-fast +test-insttest-rv64d-linux-MinorCPU-RISCV-i386-fast +test-insttest-rv64f-linux-MinorCPU-RISCV-i386-fast +test-insttest-rv64i-linux-MinorCPU-RISCV-i386-fast +test-insttest-rv64m-linux-MinorCPU-RISCV-i386-fast +test-insttest-rv64i-linux-AtomicSimpleCPU-RISCV-i386-fast +test-insttest-rv64i-linux-TimingSimpleCPU-RISCV-i386-fast +test-insttest-rv64i-linux-DerivO3CPU-RISCV-i386-fast +test-insttest-linux-AtomicSimpleCPU-SPARC-i386-fast +test-insttest-linux-TimingSimpleCPU-SPARC-i386-fast diff --git a/tests/gem5/insttest_se/ref/riscv/linux/insttest-rv64a/simout b/tests/gem5/insttest_se/ref/riscv/linux/insttest-rv64a/simout new file mode 100644 index 000000000..4e943d0e7 --- /dev/null +++ b/tests/gem5/insttest_se/ref/riscv/linux/insttest-rv64a/simout @@ -0,0 +1,41 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + + +Global frequency set at 1000000000000 ticks per second +**** REAL SIMULATION **** +lr.w/sc.w: PASS +sc.w, no preceding lr.d: PASS +amoswap.w: PASS +amoswap.w, sign extend: PASS +amoswap.w, truncate: PASS +amoadd.w: PASS +amoadd.w, truncate/overflow: PASS +amoadd.w, sign extend: PASS +amoxor.w, truncate: PASS +amoxor.w, sign extend: PASS +amoand.w, truncate: PASS +amoand.w, sign extend: PASS +amoor.w, truncate: PASS +amoor.w, sign extend: PASS +amomin.w, truncate: PASS +amomin.w, sign extend: PASS +amomax.w, truncate: PASS +amomax.w, sign extend: PASS +amominu.w, truncate: PASS +amominu.w, sign extend: PASS +amomaxu.w, truncate: PASS +amomaxu.w, sign extend: PASS +lr.d/sc.d: PASS +sc.d, no preceding lr.d: PASS +amoswap.d: PASS +amoadd.d: PASS +amoadd.d, overflow: PASS +amoxor.d (1): PASS +amoxor.d (0): PASS +amoand.d: PASS +amoor.d: PASS +amomin.d: PASS +amomax.d: PASS +amominu.d: PASS +amomaxu.d: PASS diff --git a/tests/gem5/insttest_se/ref/riscv/linux/insttest-rv64c/simout b/tests/gem5/insttest_se/ref/riscv/linux/insttest-rv64c/simout new file mode 100644 index 000000000..69e024f77 --- /dev/null +++ b/tests/gem5/insttest_se/ref/riscv/linux/insttest-rv64c/simout @@ -0,0 +1,60 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + + +Global frequency set at 1000000000000 ticks per second +**** REAL SIMULATION **** +c.lwsp: PASS +c.ldsp: PASS +c.fldsp: PASS +c.swsp: PASS +c.sdsp: PASS +c.fsdsp: PASS +c.lw, positive: PASS +c.lw, negative: PASS +c.ld: PASS +c.fld: PASS +c.sw: PASS +c.sd: PASS +c.fsd: PASS +c.j: PASS +c.jr: PASS +c.jalr: PASS +c.beqz, zero: PASS +c.beqz, not zero: PASS +c.bnez, not zero: PASS +c.bnez, zero: PASS +c.li: PASS +c.li, sign extend: PASS +c.lui: PASS +c.addi: PASS +c.addiw: PASS +c.addiw, overflow: PASS +c.addiw, truncate: PASS +c.addi16sp: PASS +c.addi4spn: PASS +c.slli: PASS +c.slli, overflow: PASS +c.srli: PASS +c.srli, overflow: PASS +c.srli, -1: PASS +c.srai: PASS +c.srai, overflow: PASS +c.srai, -1: PASS +c.andi (0): PASS +c.andi (1): PASS +c.mv: PASS +c.add: PASS +c.and (0): PASS +c.and (-1): PASS +c.or (1): PASS +c.or (A): PASS +c.xor (1): PASS +c.xor (0): PASS +c.sub: PASS +c.addw: PASS +c.addw, overflow: PASS +c.addw, truncate: PASS +c.subw: PASS +c.subw, "overflow": PASS +c.subw, truncate: PASS diff --git a/tests/gem5/insttest_se/ref/riscv/linux/insttest-rv64d/simout b/tests/gem5/insttest_se/ref/riscv/linux/insttest-rv64d/simout new file mode 100644 index 000000000..a6ace25c9 --- /dev/null +++ b/tests/gem5/insttest_se/ref/riscv/linux/insttest-rv64d/simout @@ -0,0 +1,218 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + + +Global frequency set at 1000000000000 ticks per second +**** REAL SIMULATION **** +fld: PASS +fsd: PASS +fmadd.d: PASS +fmadd.d, quiet NaN: PASS +fmadd.d, signaling NaN: PASS +fmadd.d, infinity: PASS +fmadd.d, -infinity: PASS +fmsub.d: PASS +fmsub.d, quiet NaN: PASS +fmsub.d, signaling NaN: PASS +fmsub.d, infinity: PASS +fmsub.d, -infinity: PASS +fmsub.d, subtract infinity: PASS +fnmsub.d: PASS +fnmsub.d, quiet NaN: PASS +fnmsub.d, signaling NaN: PASS +fnmsub.d, infinity: PASS +fnmsub.d, -infinity: PASS +fnmsub.d, subtract infinity: PASS +fnmadd.d: PASS +fnmadd.d, quiet NaN: PASS +fnmadd.d, signaling NaN: PASS +fnmadd.d, infinity: PASS +fnmadd.d, -infinity: PASS +fadd.d: PASS +fadd.d, quiet NaN: PASS +fadd.d, signaling NaN: PASS +fadd.d, infinity: PASS +fadd.d, -infinity: PASS +fsub.d: PASS +fsub.d, quiet NaN: PASS +fsub.d, signaling NaN: PASS +fsub.d, infinity: PASS +fsub.d, -infinity: PASS +fsub.d, subtract infinity: PASS +fmul.d: PASS +fmul.d, quiet NaN: PASS +fmul.d, signaling NaN: PASS +fmul.d, infinity: PASS +fmul.d, -infinity: PASS +fmul.d, 0*infinity: PASS +fmul.d, overflow: PASS +fmul.d, underflow: PASS +fdiv.d: PASS +fdiv.d, quiet NaN: PASS +fdiv.d, signaling NaN: PASS +fdiv.d/0: PASS +fdiv.d/infinity: PASS +fdiv.d, infinity/infinity: PASS +fdiv.d, 0/0: PASS +fdiv.d, infinity/0: PASS +fdiv.d, 0/infinity: PASS +fdiv.d, underflow: PASS +fdiv.d, overflow: PASS +fsqrt.d: PASS +fsqrt.d, NaN: PASS +fsqrt.d, quiet NaN: PASS +fsqrt.d, signaling NaN: PASS +fsqrt.d, infinity: PASS +fsgnj.d, ++: PASS +fsgnj.d, +-: PASS +fsgnj.d, -+: PASS +fsgnj.d, --: PASS +fsgnj.d, quiet NaN: PASS +fsgnj.d, signaling NaN: PASS +fsgnj.d, inject NaN: PASS +fsgnj.d, inject -NaN: PASS +fsgnjn.d, ++: PASS +fsgnjn.d, +-: PASS +fsgnjn.d, -+: PASS +fsgnjn.d, --: PASS +fsgnjn.d, quiet NaN: PASS +fsgnjn.d, signaling NaN: PASS +fsgnjn.d, inject NaN: PASS +fsgnjn.d, inject NaN: PASS +fsgnjx.d, ++: PASS +fsgnjx.d, +-: PASS +fsgnjx.d, -+: PASS +fsgnjx.d, --: PASS +fsgnjx.d, quiet NaN: PASS +fsgnjx.d, signaling NaN: PASS +fsgnjx.d, inject NaN: PASS +fsgnjx.d, inject NaN: PASS +fmin.d: PASS +fmin.d, -infinity: PASS +fmin.d, infinity: PASS +fmin.d, quiet NaN first: PASS +fmin.d, quiet NaN second: PASS +fmin.d, quiet NaN both: PASS +fmin.d, signaling NaN first: PASS +fmin.d, signaling NaN second: PASS +fmin.d, signaling NaN both: PASS +fmax.d: PASS +fmax.d, -infinity: PASS +fmax.d, infinity: PASS +fmax.d, quiet NaN first: PASS +fmax.d, quiet NaN second: PASS +fmax.d, quiet NaN both: PASS +fmax.d, signaling NaN first: PASS +fmax.d, signaling NaN second: PASS +fmax.d, signaling NaN both: PASS +fcvt.s.d: PASS +fcvt.s.d, quiet NaN: PASS +fcvt.s.d, signaling NaN: PASS +fcvt.s.d, infinity: PASS +fcvt.s.d, overflow: PASS +fcvt.s.d, underflow: PASS +fcvt.d.s: PASS +fcvt.d.s, quiet NaN: PASS +fcvt.d.s, signaling NaN: PASS +fcvt.d.s, infinity: PASS +feq.d, equal: PASS +feq.d, not equal: PASS +feq.d, 0 == -0: PASS +feq.d, quiet NaN first: PASS +feq.d, quiet NaN second: PASS +feq.d, quiet NaN both: PASS +feq.d, signaling NaN first: PASS +feq.d, signaling NaN second: PASS +feq.d, signaling NaN both: PASS +flt.d, equal: PASS +flt.d, less: PASS +flt.d, greater: PASS +flt.d, quiet NaN first: PASS +flt.d, quiet NaN second: PASS +flt.d, quiet NaN both: PASS +flt.d, signaling NaN first: PASS +flt.d, signaling NaN second: PASS +flt.d, signaling NaN both: PASS +fle.d, equal: PASS +fle.d, less: PASS +fle.d, greater: PASS +fle.d, 0 == -0: PASS +fle.d, quiet NaN first: PASS +fle.d, quiet NaN second: PASS +fle.d, quiet NaN both: PASS +fle.d, signaling NaN first: PASS +fle.d, signaling NaN second: PASS +fle.d, signaling NaN both: PASS +fclass.d, -infinity: PASS +fclass.d, -normal: PASS +fclass.d, -subnormal: PASS +fclass.d, -0.0: PASS +fclass.d, 0.0: PASS +fclass.d, subnormal: PASS +fclass.d, normal: PASS +fclass.d, infinity: PASS +fclass.d, signaling NaN: PASS +fclass.s, quiet NaN: PASS +fcvt.w.d, truncate positive: PASS +fcvt.w.d, truncate negative: PASS +fcvt.w.d, 0.0: PASS +fcvt.w.d, -0.0: PASS +fcvt.w.d, overflow: PASS +fcvt.w.d, underflow: PASS +fcvt.w.d, infinity: PASS +fcvt.w.d, -infinity: PASS +fcvt.w.d, quiet NaN: PASS +fcvt.w.d, quiet -NaN: PASS +fcvt.w.d, signaling NaN: PASS +fcvt.wu.d, truncate positive: PASS +fcvt.wu.d, truncate negative: PASS +fcvt.wu.d, 0.0: PASS +fcvt.wu.d, -0.0: PASS +fcvt.wu.d, overflow: PASS +fcvt.wu.d, underflow: PASS +fcvt.wu.d, infinity: PASS +fcvt.wu.d, -infinity: PASS +fcvt.wu.d, quiet NaN: PASS +fcvt.wu.d, quiet -NaN: PASS +fcvt.wu.d, signaling NaN: PASS +fcvt.d.w, 0: PASS +fcvt.d.w, negative: PASS +fcvt.d.w, truncate: PASS +fcvt.d.wu, 0: PASS +fcvt.d.wu: PASS +fcvt.d.wu, truncate: PASS +fcvt.l.d, truncate positive: PASS +fcvt.l.d, truncate negative: PASS +fcvt.l.d, 0.0: PASS +fcvt.l.d, -0.0: PASS +fcvt.l.d, 32-bit overflow: PASS +fcvt.l.d, overflow: PASS +fcvt.l.d, underflow: PASS +fcvt.l.d, infinity: PASS +fcvt.l.d, -infinity: PASS +fcvt.l.d, quiet NaN: PASS +fcvt.l.d, quiet -NaN: PASS +fcvt.l.d, signaling NaN: PASS +fcvt.lu.d, truncate positive: PASS +fcvt.lu.d, truncate negative: PASS +fcvt.lu.d, 0.0: PASS +fcvt.lu.d, -0.0: PASS +fcvt.lu.d, 32-bit overflow: PASS +fcvt.lu.d, overflow: PASS +fcvt.lu.d, underflow: PASS +fcvt.lu.d, infinity: PASS +fcvt.lu.d, -infinity: PASS +fcvt.lu.d, quiet NaN: PASS +fcvt.lu.d, quiet -NaN: PASS +fcvt.lu.d, signaling NaN: PASS +fmv.x.d, positive: PASS +fmv.x.d, negative: PASS +fmv.x.d, 0.0: PASS +fmv.x.d, -0.0: PASS +fcvt.d.l, 0: PASS +fcvt.d.l, negative: PASS +fcvt.d.l, 32-bit truncate: PASS +fcvt.d.lu, 0: PASS +fcvt.d.lu: PASS +fcvt.d.lu, 32-bit truncate: PASS +fmv.d.x: PASS diff --git a/tests/gem5/insttest_se/ref/riscv/linux/insttest-rv64f/simout b/tests/gem5/insttest_se/ref/riscv/linux/insttest-rv64f/simout new file mode 100644 index 000000000..c48f56994 --- /dev/null +++ b/tests/gem5/insttest_se/ref/riscv/linux/insttest-rv64f/simout @@ -0,0 +1,214 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + + +Global frequency set at 1000000000000 ticks per second +**** REAL SIMULATION **** +clear fsflags: PASS +flw: PASS +fsw: PASS +fmadd.s: PASS +fmadd.s, quiet NaN: PASS +fmadd.s, signaling NaN: PASS +fmadd.s, infinity: PASS +fmadd.s, -infinity: PASS +fmsub.s: PASS +fmsub.s, quiet NaN: PASS +fmsub.s, signaling NaN: PASS +fmsub.s, infinity: PASS +fmsub.s, -infinity: PASS +fmsub.s, subtract infinity: PASS +fnmsub.s: PASS +fnmsub.s, quiet NaN: PASS +fnmsub.s, signaling NaN: PASS +fnmsub.s, infinity: PASS +fnmsub.s, -infinity: PASS +fnmsub.s, subtract infinity: PASS +fnmadd.s: PASS +fnmadd.s, quiet NaN: PASS +fnmadd.s, signaling NaN: PASS +fnmadd.s, infinity: PASS +fnmadd.s, -infinity: PASS +fadd.s: PASS +fadd.s, quiet NaN: PASS +fadd.s, signaling NaN: PASS +fadd.s, infinity: PASS +fadd.s, -infinity: PASS +fsub.s: PASS +fsub.s, quiet NaN: PASS +fsub.s, signaling NaN: PASS +fsub.s, infinity: PASS +fsub.s, -infinity: PASS +fsub.s, subtract infinity: PASS +fmul.s: PASS +fmul.s, quiet NaN: PASS +fmul.s, signaling NaN: PASS +fmul.s, infinity: PASS +fmul.s, -infinity: PASS +fmul.s, 0*infinity: PASS +fmul.s, overflow: PASS +fmul.s, underflow: PASS +fdiv.s: PASS +fdiv.s, quiet NaN: PASS +fdiv.s, signaling NaN: PASS +fdiv.s/0: PASS +fdiv.s/infinity: PASS +fdiv.s, infinity/infinity: PASS +fdiv.s, 0/0: PASS +fdiv.s, infinity/0: PASS +fdiv.s, 0/infinity: PASS +fdiv.s, underflow: PASS +fdiv.s, overflow: PASS +fsqrt.s: PASS +fsqrt.s, NaN: PASS +fsqrt.s, quiet NaN: PASS +fsqrt.s, signaling NaN: PASS +fsqrt.s, infinity: PASS +fsgnj.s, ++: PASS +fsgnj.s, +-: PASS +fsgnj.s, -+: PASS +fsgnj.s, --: PASS +fsgnj.s, quiet NaN: PASS +fsgnj.s, signaling NaN: PASS +fsgnj.s, inject NaN: PASS +fsgnj.s, inject -NaN: PASS +fsgnjn.s, ++: PASS +fsgnjn.s, +-: PASS +fsgnjn.s, -+: PASS +fsgnjn.s, --: PASS +fsgnjn.s, quiet NaN: PASS +fsgnjn.s, signaling NaN: PASS +fsgnjn.s, inject NaN: PASS +fsgnjn.s, inject NaN: PASS +fsgnjx.s, ++: PASS +fsgnjx.s, +-: PASS +fsgnjx.s, -+: PASS +fsgnjx.s, --: PASS +fsgnjx.s, quiet NaN: PASS +fsgnjx.s, signaling NaN: PASS +fsgnjx.s, inject NaN: PASS +fsgnjx.s, inject -NaN: PASS +fmin.s: PASS +fmin.s, -infinity: PASS +fmin.s, infinity: PASS +fmin.s, quiet NaN first: PASS +fmin.s, quiet NaN second: PASS +fmin.s, quiet NaN both: PASS +fmin.s, signaling NaN first: PASS +fmin.s, signaling NaN second: PASS +fmin.s, signaling NaN both: PASS +fmax.s: PASS +fmax.s, -infinity: PASS +fmax.s, infinity: PASS +fmax.s, quiet NaN first: PASS +fmax.s, quiet NaN second: PASS +fmax.s, quiet NaN both: PASS +fmax.s, signaling NaN first: PASS +fmax.s, signaling NaN second: PASS +fmax.s, signaling NaN both: PASS +fcvt.w.s, truncate positive: PASS +fcvt.w.s, truncate negative: PASS +fcvt.w.s, 0.0: PASS +fcvt.w.s, -0.0: PASS +fcvt.w.s, overflow: PASS +fcvt.w.s, underflow: PASS +fcvt.w.s, infinity: PASS +fcvt.w.s, -infinity: PASS +fcvt.w.s, quiet NaN: PASS +fcvt.w.s, quiet -NaN: PASS +fcvt.w.s, signaling NaN: PASS +fcvt.wu.s, truncate positive: PASS +fcvt.wu.s, truncate negative: PASS +fcvt.wu.s, 0.0: PASS +fcvt.wu.s, -0.0: PASS +fcvt.wu.s, overflow: PASS +fcvt.wu.s, underflow: PASS +fcvt.wu.s, infinity: PASS +fcvt.wu.s, -infinity: PASS +fcvt.wu.s, quiet NaN: PASS +fcvt.wu.s, quiet -NaN: PASS +fcvt.wu.s, signaling NaN: PASS +fmv.x.s, positive: PASS +fmv.x.s, negative: PASS +fmv.x.s, 0.0: PASS +fmv.x.s, -0.0: PASS +feq.s, equal: PASS +feq.s, not equal: PASS +feq.s, 0 == -0: PASS +feq.s, quiet NaN first: PASS +feq.s, quiet NaN second: PASS +feq.s, quiet NaN both: PASS +feq.s, signaling NaN first: PASS +feq.s, signaling NaN second: PASS +feq.s, signaling NaN both: PASS +flt.s, equal: PASS +flt.s, less: PASS +flt.s, greater: PASS +flt.s, quiet NaN first: PASS +flt.s, quiet NaN second: PASS +flt.s, quiet NaN both: PASS +flt.s, signaling NaN first: PASS +flt.s, signaling NaN second: PASS +flt.s, signaling NaN both: PASS +fle.s, equal: PASS +fle.s, less: PASS +fle.s, greater: PASS +fle.s, 0 == -0: PASS +fle.s, quiet NaN first: PASS +fle.s, quiet NaN second: PASS +fle.s, quiet NaN both: PASS +fle.s, signaling NaN first: PASS +fle.s, signaling NaN second: PASS +fle.s, signaling NaN both: PASS +fclass.s, -infinity: PASS +fclass.s, -normal: PASS +fclass.s, -subnormal: PASS +fclass.s, -0.0: PASS +fclass.s, 0.0: PASS +fclass.s, subnormal: PASS +fclass.s, normal: PASS +fclass.s, infinity: PASS +fclass.s, signaling NaN: PASS +fclass.s, quiet NaN: PASS +fcvt.s.w, 0: PASS +fcvt.s.w, negative: PASS +fcvt.s.w, truncate: PASS +fcvt.s.wu, 0: PASS +fcvt.s.wu: PASS +fcvt.s.wu, truncate: PASS +fmv.s.x: PASS +fmv.s.x, truncate: PASS +fsrm: PASS +fsflags: PASS +fscsr: PASS +restore initial round mode: PASS +fcvt.l.s, truncate positive: PASS +fcvt.l.s, truncate negative: PASS +fcvt.l.s, 0.0: PASS +fcvt.l.s, -0.0: PASS +fcvt.l.s, 32-bit overflow: PASS +fcvt.l.s, overflow: PASS +fcvt.l.s, underflow: PASS +fcvt.l.s, infinity: PASS +fcvt.l.s, -infinity: PASS +fcvt.l.s, quiet NaN: PASS +fcvt.l.s, quiet -NaN: PASS +fcvt.l.s, signaling NaN: PASS +fcvt.lu.s, truncate positive: PASS +fcvt.lu.s, truncate negative: PASS +fcvt.lu.s, 0.0: PASS +fcvt.lu.s, -0.0: PASS +fcvt.lu.s, 32-bit overflow: PASS +fcvt.lu.s, overflow: PASS +fcvt.lu.s, underflow: PASS +fcvt.lu.s, infinity: PASS +fcvt.lu.s, -infinity: PASS +fcvt.lu.s, quiet NaN: PASS +fcvt.lu.s, quiet -NaN: PASS +fcvt.lu.s, signaling NaN: PASS +fcvt.s.l, 0: PASS +fcvt.s.l, negative: PASS +fcvt.s.l, 32-bit truncate: PASS +fcvt.s.lu, 0: PASS +fcvt.s.lu: PASS +fcvt.s.lu, 32-bit truncate: PASS diff --git a/tests/gem5/insttest_se/ref/riscv/linux/insttest-rv64i/simout b/tests/gem5/insttest_se/ref/riscv/linux/insttest-rv64i/simout new file mode 100644 index 000000000..e12099f38 --- /dev/null +++ b/tests/gem5/insttest_se/ref/riscv/linux/insttest-rv64i/simout @@ -0,0 +1,164 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + + +Global frequency set at 1000000000000 ticks per second +**** REAL SIMULATION **** +lui: PASS +lui, negative: PASS +auipc: 0x1856C +auipc: PASS +jal: PASS +jalr: PASS +beq, equal: PASS +beq, not equal: PASS +bne, equal: PASS +bne, not equal: PASS +blt, less: PASS +blt, equal: PASS +blt, greater: PASS +bge, less: PASS +bge, equal: PASS +bge, greater: PASS +bltu, greater: PASS +bltu, equal: PASS +bltu, less: PASS +bgeu, greater: PASS +bgeu, equal: PASS +bgeu, less: PASS +lb, positive: PASS +lb, negative: PASS +lh, positive: PASS +lh, negative: PASS +lw, positive: PASS +lw, negative: PASS +lbu: PASS +lhu: PASS +sb: PASS +sh: PASS +sw: PASS +addi: PASS +addi, overflow: PASS +slti, true: PASS +slti, false: PASS +sltiu, false: PASS +sltiu, true: PASS +sltiu, sext: PASS +xori (1): PASS +xori (0): PASS +ori (1): PASS +ori (A): PASS +andi (0): PASS +andi (1): PASS +slli, general: PASS +slli, erase: PASS +srli, general: PASS +srli, erase: PASS +srli, negative: PASS +srai, general: PASS +srai, erase: PASS +srai, negative: PASS +add: PASS +add, overflow: PASS +sub: PASS +sub, "overflow": PASS +sll, general: PASS +sll, erase: PASS +slt, true: PASS +slt, false: PASS +sltu, false: PASS +sltu, true: PASS +xor (1): PASS +xor (0): PASS +srl, general: PASS +srl, erase: PASS +srl, negative: PASS +sra, general: PASS +sra, erase: PASS +sra, negative: PASS +or (1): PASS +or (A): PASS +and (0): PASS +and (-1): PASS +Bytes written: 15 +open, write: PASS +access F_OK: PASS +access R_OK: PASS +access W_OK: PASS +access X_OK: PASS +stat: + st_dev = 66305 + st_ino = 19684698 + st_mode = 33188 + st_nlink = 1 + st_uid = 1019 + st_gid = 1020 + st_rdev = 0 + st_size = 15 + st_blksize = 8192 + st_blocks = 8 +fstat: + st_dev = 66305 + st_ino = 19684698 + st_mode = 33188 + st_nlink = 1 + st_uid = 1019 + st_gid = 1020 + st_rdev = 0 + st_size = 15 + st_blksize = 8192 + st_blocks = 8 +open, stat: PASS +Bytes read: 15 +String read: this is a test +open, read, unlink: PASS +times: + tms_utime = 0 + tms_stime = 0 + tms_cutime = 0 + tms_cstime = 0 +times: FAIL (expected 1; found 0) +timeval: + tv_sec = 1000000000 + tv_usec = 126 +gettimeofday: PASS +Cycles: 257794 +rdcycle: PASS +Time: 1582249831 +rdtime: PASS +Instructions Retired: 215961 +rdinstret: PASS +lwu: PASS +ld: PASS +sd: PASS +addiw: PASS +addiw, overflow: PASS +addiw, truncate: PASS +slliw, general: PASS +slliw, erase: PASS +slliw, truncate: PASS +srliw, general: PASS +srliw, erase: PASS +srliw, negative: PASS +srliw, truncate: PASS +sraiw, general: PASS +sraiw, erase: PASS +sraiw, negative: PASS +sraiw, truncate: PASS +addw: PASS +addw, overflow: PASS +addw, truncate: PASS +subw: PASS +subw, "overflow": PASS +subw, truncate: PASS +sllw, general: PASS +sllw, erase: PASS +sllw, truncate: PASS +srlw, general: PASS +srlw, erase: PASS +srlw, negative: PASS +srlw, truncate: PASS +sraw, general: PASS +sraw, erase: PASS +sraw, negative: PASS +sraw, truncate: PASS diff --git a/tests/gem5/insttest_se/ref/riscv/linux/insttest-rv64m/simout b/tests/gem5/insttest_se/ref/riscv/linux/insttest-rv64m/simout new file mode 100644 index 000000000..1bbc4fa91 --- /dev/null +++ b/tests/gem5/insttest_se/ref/riscv/linux/insttest-rv64m/simout @@ -0,0 +1,43 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + + +Global frequency set at 1000000000000 ticks per second +**** REAL SIMULATION **** +mul: PASS +mul, overflow: PASS +mulh: PASS +mulh, negative: PASS +mulh, all bits set: PASS +mulhsu, all bits set: PASS +mulhsu: PASS +mulhu: PASS +mulhu, all bits set: PASS +div: PASS +div/0: PASS +div, overflow: PASS +divu: PASS +divu/0: PASS +divu, "overflow": PASS +rem: PASS +rem/0: PASS +rem, overflow: PASS +remu: PASS +remu/0: PASS +remu, "overflow": PASS +mulw, truncate: PASS +mulw, overflow: PASS +divw, truncate: PASS +divw/0: PASS +divw, overflow: PASS +divuw, truncate: PASS +divuw/0: PASS +divuw, "overflow": PASS +divuw, sign extend: PASS +remw, truncate: PASS +remw/0: PASS +remw, overflow: PASS +remuw, truncate: PASS +remuw/0: PASS +remuw, "overflow": PASS +remuw, sign extend: PASS diff --git a/tests/gem5/insttest_se/ref/sparc/linux/simout b/tests/gem5/insttest_se/ref/sparc/linux/simout new file mode 100755 index 000000000..bf2b3f4bd --- /dev/null +++ b/tests/gem5/insttest_se/ref/sparc/linux/simout @@ -0,0 +1,23 @@ +Redirecting stdout to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic/simout +Redirecting stderr to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Apr 3 2017 18:41:19 +gem5 started Apr 3 2017 18:41:41 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 64897 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/02.insttest/sparc/linux/simple-atomic + +Global frequency set at 1000000000000 ticks per second +Begining test of difficult SPARC instructions... +LDSTUB: Passed +SWAP: Passed +CAS FAIL: Passed +CAS WORK: Passed +CASX FAIL: Passed +CASX WORK: Passed +LDTX: Passed +LDTW: Passed +STTW: Passed +Done +Exiting @ tick 7612000 because exiting with last active thread context diff --git a/tests/gem5/insttest_se/test.py b/tests/gem5/insttest_se/test.py new file mode 100644 index 000000000..e81f943b2 --- /dev/null +++ b/tests/gem5/insttest_se/test.py @@ -0,0 +1,78 @@ +# Copyright (c) 2020 The Regents of the University of California +# All Rights Reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Bobby R. Bruce + +''' +Test file for the insttest binary running on the RISCV and SPARC +''' +from testlib import * + +test_progs = { + 'riscv': ('insttest-rv64a', 'insttest-rv64c', 'insttest-rv64d', + 'insttest-rv64f', 'insttest-rv64i', 'insttest-rv64m'), + 'sparc': ('insttest',) +} +#o3-timing simple-atomic simple-timing +cpu_types = { + 'riscv' : ('AtomicSimpleCPU', 'TimingSimpleCPU', 'DerivO3CPU', 'MinorCPU'), + 'sparc' : ('AtomicSimpleCPU', 'TimingSimpleCPU') +} +supported_os = { + 'riscv' : ('linux',), + 'sparc' : ('linux',) +} + +urlbase = 'http://dist.gem5.org/dist/current/test-progs/insttest/bin/' +for isa in test_progs: + for binary in test_progs[isa]: + for operating_s in supported_os[isa]: + import os + url = urlbase + isa + '/' + operating_s + '/' + binary + path = joinpath(absdirpath(__file__), '..', 'test-progs', binary, + 'bin', isa, operating_s) + try: + program = DownloadedProgram(url, path, binary) + except: + continue + + ref_path = joinpath(getcwd(), 'ref', isa, operating_s, binary) + verifiers = ( + verifier.MatchStdoutNoPerf(joinpath(ref_path, 'simout')), + ) + + for cpu in cpu_types[isa]: + + gem5_verify_config( + name='test-'+binary + '-' + operating_s + '-' + cpu, + fixtures=(program,), + verifiers=verifiers, + config=joinpath(config.base_dir, 'configs', + 'example','se.py'), + config_args=['--cmd', joinpath(path, binary), + '--cpu-type', cpu, '--caches'], + valid_isas=(isa.upper(),), + ) -- 2.30.2