From 4c9fde87d170fc8d4b729581b055407553951e4c Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 12 Jun 2019 08:48:45 -0700 Subject: [PATCH] Revert "Add "-W' wire delay arg to abc9, use from synth_xilinx" This reverts commit 2dffa4685b830313204f5d04314a14ed6ecac8ec. --- frontends/verilog/verilog_lexer.l | 5 +++++ passes/techmap/abc9.cc | 18 +++++------------- techlibs/xilinx/synth_xilinx.cc | 2 +- 3 files changed, 11 insertions(+), 14 deletions(-) diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index 9558bbfb9..3c612472d 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -311,6 +311,11 @@ supply1 { return TOK_SUPPLY1; } return TOK_ID; } +"$"(info|warning|error|fatal) { + frontend_verilog_yylval.string = new std::string(yytext); + return TOK_ELAB_TASK; +} + "$signed" { return TOK_TO_SIGNED; } "$unsigned" { return TOK_TO_UNSIGNED; } diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 19157adc6..af9439e41 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -25,7 +25,7 @@ #define ABC_COMMAND_LIB "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put" #define ABC_COMMAND_CTR "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put; buffer; upsize {D}; dnsize {D}; stime -p" //#define ABC_COMMAND_LUT "strash; ifraig; scorr; dc2; dretime; strash; dch -f; if; mfs2" -#define ABC_COMMAND_LUT "&st; &sweep; &scorr; "/*"&dc2; */"&retime; &dch -f; &ps -l; &if {W} -v; &ps -l" +#define ABC_COMMAND_LUT "&st; &sweep; &scorr; "/*"&dc2; */"&retime; &dch -f; &ps -l; &if -W 160 -v; &ps -l" #define ABC_COMMAND_SOP "strash; ifraig; scorr; dc2; dretime; strash; dch -f; cover {I} {P}" #define ABC_COMMAND_DFL "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put" @@ -272,8 +272,7 @@ failed: void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::string script_file, std::string exe_file, std::string liberty_file, std::string constr_file, bool cleanup, vector lut_costs, bool dff_mode, std::string clk_str, bool keepff, std::string delay_target, std::string sop_inputs, std::string sop_products, std::string lutin_shared, bool fast_mode, - const std::vector &cells, bool show_tempdir, bool sop_mode, std::string box_file, std::string lut_file, - std::string wire_delay) + const std::vector &cells, bool show_tempdir, bool sop_mode, std::string box_file, std::string lut_file) { module = current_module; map_autoidx = autoidx++; @@ -388,9 +387,6 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri for (size_t pos = abc_script.find("{S}"); pos != std::string::npos; pos = abc_script.find("{S}", pos)) abc_script = abc_script.substr(0, pos) + lutin_shared + abc_script.substr(pos+3); - for (size_t pos = abc_script.find("{W}"); pos != std::string::npos; pos = abc_script.find("{W}", pos)) - abc_script = abc_script.substr(0, pos) + wire_delay + abc_script.substr(pos+3); - abc_script += stringf("; &write %s/output.aig", tempdir_name.c_str()); abc_script = add_echos_to_abc_cmd(abc_script); @@ -964,7 +960,7 @@ struct Abc9Pass : public Pass { std::string exe_file = proc_self_dirname() + "yosys-abc"; #endif std::string script_file, liberty_file, constr_file, clk_str, box_file, lut_file; - std::string delay_target, sop_inputs, sop_products, lutin_shared = "-S 1", wire_delay; + std::string delay_target, sop_inputs, sop_products, lutin_shared = "-S 1"; bool fast_mode = false, dff_mode = false, keepff = false, cleanup = true; bool show_tempdir = false, sop_mode = false; vector lut_costs; @@ -1218,10 +1214,6 @@ struct Abc9Pass : public Pass { box_file = std::string(pwd) + "/" + box_file; continue; } - if (arg == "-W" && argidx+1 < args.size()) { - wire_delay = "-S " + args[++argidx]; - continue; - } break; } extra_args(args, argidx, design); @@ -1264,7 +1256,7 @@ struct Abc9Pass : public Pass { if (!dff_mode || !clk_str.empty()) { abc9_module(design, mod, script_file, exe_file, liberty_file, constr_file, cleanup, lut_costs, dff_mode, clk_str, keepff, delay_target, sop_inputs, sop_products, lutin_shared, fast_mode, mod->selected_cells(), show_tempdir, sop_mode, - box_file, lut_file, wire_delay); + box_file, lut_file); continue; } @@ -1410,7 +1402,7 @@ struct Abc9Pass : public Pass { en_sig = assign_map(std::get<3>(it.first)); abc9_module(design, mod, script_file, exe_file, liberty_file, constr_file, cleanup, lut_costs, !clk_sig.empty(), "$", keepff, delay_target, sop_inputs, sop_products, lutin_shared, fast_mode, it.second, show_tempdir, sop_mode, - box_file, lut_file, wire_delay); + box_file, lut_file); assign_map.set(mod); } } diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index f966115cd..f5f8c43e0 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -297,7 +297,7 @@ struct SynthXilinxPass : public ScriptPass if (check_label("map_luts")) { if (abc == "abc9") - run(abc + " -lut +/xilinx/abc.lut -box +/xilinx/abc.box -W 160" + string(retime ? " -dff" : "")); + run(abc + " -lut +/xilinx/abc.lut -box +/xilinx/abc.box" + string(retime ? " -dff" : "")); else if (help_mode) run(abc + " -luts 2:2,3,6:5,10,20 [-dff]"); else -- 2.30.2