From 4cb4640c2c34f550c7e78c5b9d456fc3ec5b6484 Mon Sep 17 00:00:00 2001 From: Alan Lawrence Date: Tue, 8 Sep 2015 19:43:39 +0000 Subject: [PATCH] ARM/AArch64 Testsuite] Add float16 lane_f16_indices tests PR target/63870 * gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f16_indices_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f16_indices_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f16_indices_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f16_indices_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f16_indices_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f16_indices_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f16_indices_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f16_indices_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f16_indices_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f16_indices_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f16_indices_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f16_indices_1.c: New. From-SVN: r227557 --- gcc/testsuite/ChangeLog | 16 ++++++++++++++++ .../advsimd-intrinsics/vld2_lane_f16_indices_1.c | 16 ++++++++++++++++ .../vld2q_lane_f16_indices_1.c | 16 ++++++++++++++++ .../advsimd-intrinsics/vld3_lane_f16_indices_1.c | 16 ++++++++++++++++ .../vld3q_lane_f16_indices_1.c | 16 ++++++++++++++++ .../advsimd-intrinsics/vld4_lane_f16_indices_1.c | 16 ++++++++++++++++ .../vld4q_lane_f16_indices_1.c | 16 ++++++++++++++++ .../advsimd-intrinsics/vst2_lane_f16_indices_1.c | 15 +++++++++++++++ .../vst2q_lane_f16_indices_1.c | 15 +++++++++++++++ .../advsimd-intrinsics/vst3_lane_f16_indices_1.c | 15 +++++++++++++++ .../vst3q_lane_f16_indices_1.c | 15 +++++++++++++++ .../advsimd-intrinsics/vst4_lane_f16_indices_1.c | 15 +++++++++++++++ .../vst4q_lane_f16_indices_1.c | 15 +++++++++++++++ 13 files changed, 202 insertions(+) create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f16_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f16_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f16_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f16_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f16_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f16_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f16_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f16_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f16_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f16_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f16_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f16_indices_1.c diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index ceeeb5d5f9a..74652c315fb 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,19 @@ +2015-09-08 Alan Lawrence + + PR target/63870 + * gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f16_indices_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f16_indices_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f16_indices_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f16_indices_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f16_indices_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f16_indices_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f16_indices_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f16_indices_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f16_indices_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f16_indices_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f16_indices_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f16_indices_1.c: New. + 2015-09-08 Alan Lawrence * gcc.target/aarch64/advsimd-intrinsics/vcvt_f16.c: New. diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f16_indices_1.c new file mode 100644 index 00000000000..2174d6eaa8f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f16_indices_1.c @@ -0,0 +1,16 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +float16x4x2_t +f_vld2_lane_f16 (float16_t * p, float16x4x2_t v) +{ + float16x4x2_t res; + /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + res = vld2_lane_f16 (p, v, 4); + /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + res = vld2_lane_f16 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f16_indices_1.c new file mode 100644 index 00000000000..83ae82c8242 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f16_indices_1.c @@ -0,0 +1,16 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +float16x8x2_t +f_vld2q_lane_f16 (float16_t * p, float16x8x2_t v) +{ + float16x8x2_t res; + /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + res = vld2q_lane_f16 (p, v, 8); + /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + res = vld2q_lane_f16 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f16_indices_1.c new file mode 100644 index 00000000000..21b7861ba75 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f16_indices_1.c @@ -0,0 +1,16 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +float16x4x3_t +f_vld3_lane_f16 (float16_t * p, float16x4x3_t v) +{ + float16x4x3_t res; + /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + res = vld3_lane_f16 (p, v, 4); + /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + res = vld3_lane_f16 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f16_indices_1.c new file mode 100644 index 00000000000..95ec3913eef --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f16_indices_1.c @@ -0,0 +1,16 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +float16x8x3_t +f_vld3q_lane_f16 (float16_t * p, float16x8x3_t v) +{ + float16x8x3_t res; + /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + res = vld3q_lane_f16 (p, v, 8); + /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + res = vld3q_lane_f16 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f16_indices_1.c new file mode 100644 index 00000000000..bd7ecf06690 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f16_indices_1.c @@ -0,0 +1,16 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +float16x4x4_t +f_vld4_lane_f16 (float16_t * p, float16x4x4_t v) +{ + float16x4x4_t res; + /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + res = vld4_lane_f16 (p, v, 4); + /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + res = vld4_lane_f16 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f16_indices_1.c new file mode 100644 index 00000000000..c27559f4ee8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f16_indices_1.c @@ -0,0 +1,16 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +float16x8x4_t +f_vld4q_lane_f16 (float16_t * p, float16x8x4_t v) +{ + float16x8x4_t res; + /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + res = vld4q_lane_f16 (p, v, 8); + /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + res = vld4q_lane_f16 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f16_indices_1.c new file mode 100644 index 00000000000..dbf5241b591 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f16_indices_1.c @@ -0,0 +1,15 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +void +f_vst2_lane_f16 (float16_t * p, float16x4x2_t v) +{ + /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + vst2_lane_f16 (p, v, 4); + /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + vst2_lane_f16 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f16_indices_1.c new file mode 100644 index 00000000000..e3c0296534b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f16_indices_1.c @@ -0,0 +1,15 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +void +f_vst2q_lane_f16 (float16_t * p, float16x8x2_t v) +{ + /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + vst2q_lane_f16 (p, v, 8); + /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + vst2q_lane_f16 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f16_indices_1.c new file mode 100644 index 00000000000..406dfd410a1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f16_indices_1.c @@ -0,0 +1,15 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +void +f_vst3_lane_f16 (float16_t * p, float16x4x3_t v) +{ + /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + vst3_lane_f16 (p, v, 4); + /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + vst3_lane_f16 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f16_indices_1.c new file mode 100644 index 00000000000..4e8b24cff8a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f16_indices_1.c @@ -0,0 +1,15 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +void +f_vst3q_lane_f16 (float16_t * p, float16x8x3_t v) +{ + /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + vst3q_lane_f16 (p, v, 8); + /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + vst3q_lane_f16 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f16_indices_1.c new file mode 100644 index 00000000000..0fe65116712 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f16_indices_1.c @@ -0,0 +1,15 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +void +f_vst4_lane_f16 (float16_t * p, float16x4x4_t v) +{ + /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + vst4_lane_f16 (p, v, 4); + /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + vst4_lane_f16 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f16_indices_1.c new file mode 100644 index 00000000000..9a5f09aa5fa --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f16_indices_1.c @@ -0,0 +1,15 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +void +f_vst4q_lane_f16 (float16_t * p, float16x8x4_t v) +{ + /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + vst4q_lane_f16 (p, v, 8); + /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + vst4q_lane_f16 (p, v, -1); + return; +} -- 2.30.2