From 4cb716c5a23d82fa0c8ee455e5c6308ab42dff06 Mon Sep 17 00:00:00 2001 From: lkcl Date: Thu, 2 Jun 2022 17:13:53 +0100 Subject: [PATCH] --- openpower/sv/svp64_quirks.mdwn | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/openpower/sv/svp64_quirks.mdwn b/openpower/sv/svp64_quirks.mdwn index b04d05a3d..44bba6d23 100644 --- a/openpower/sv/svp64_quirks.mdwn +++ b/openpower/sv/svp64_quirks.mdwn @@ -153,6 +153,26 @@ for the type of operation (Branch, CRs, Memory, Arithmetic), and each Category has its own relevant but ultimately rational quirks. +# Twin Predication + +Twin Predication is an entirely new concept not present in any commercial +Vector ISA of the past forty years. To explain: + +* Predication on the destination of a LOAD instruction creates something + called "Vector Compressed Load" (VCOMPRESS). +* Predication on the *source* of a STORE instruction creates something + called "Vector Expanded Store" (VEXPAND). +* SVP64 allows the two to be put back-to-back. + +The above allows a reader familiar with VCOMPRESS and VEXPAND to +conceptualise what the effect of Twin Predication is, but it actually +goes much further: in *any* twin-predicated instruction (extsw, fmv) +it is possible to apply one predicate to the source register (compressing +the source element array) and another *completely separate* predicate +to the destination register, *in one instruction* and not just on Load/Stores. + + + # CR weird instructions [[sv/int_cr_predication]] is by far the biggest violator of the SVP64 -- 2.30.2