From 4cbb7cab47a3b91a12ad52baab5bbe6e4373ce73 Mon Sep 17 00:00:00 2001 From: Christophe Lyon Date: Mon, 7 Dec 2020 14:43:18 +0000 Subject: [PATCH] arm: Auto-vectorization for MVE: vneg This patch enables MVE vneg instructions for auto-vectorization. MVE vnegq insns in mve.md are modified to use 'neg' instead of unspec expression. The neg2 expander is added to vec-common.md. Existing patterns in neon.md are prefixed with neon_. It's not clear why we have different patterns for VDQW and VH in neon.md, when WDQWH handles both, and patterns with VDQ have provision for attributes for FP modes. Another question is why 2 always sets neon_abs type when it also handles neon_neq cases. 2020-12-11 Christophe Lyon gcc/ * config/arm/mve.md (mve_vnegq_f): Use 'neg' instead of unspec. (mve_vnegq_s): Likewise. * config/arm/neon.md (neg2): Rename into neon_neg2. (2): Rename into neon_2. (neon_v): Call gen_neon_2. (vashr3): Call gen_neon_neg2. (vlshr3): Call gen_neon_neg2. (neon_vneg): Call gen_neon_neg2. * config/arm/unspecs.md (VNEGQ_F, VNEGQ_S): Remove. * config/arm/vec-common.md (neg2): New expander. gcc/testsuite/ * gcc.target/arm/simd/mve-vneg.c: Add tests for vneg. --- gcc/config/arm/mve.md | 6 +-- gcc/config/arm/neon.md | 12 ++--- gcc/config/arm/unspecs.md | 2 - gcc/config/arm/vec-common.md | 6 +++ gcc/testsuite/gcc.target/arm/simd/mve-vneg.c | 49 ++++++++++++++++++++ 5 files changed, 63 insertions(+), 12 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arm/simd/mve-vneg.c diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 86d7fc64763..b4c5a1e27c4 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -271,8 +271,7 @@ (define_insn "mve_vnegq_f" [ (set (match_operand:MVE_0 0 "s_register_operand" "=w") - (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")] - VNEGQ_F)) + (neg:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w"))) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "vneg.f%# %q0, %q1" @@ -422,8 +421,7 @@ (define_insn "mve_vnegq_s" [ (set (match_operand:MVE_2 0 "s_register_operand" "=w") - (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")] - VNEGQ_S)) + (neg:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w"))) ] "TARGET_HAVE_MVE" "vneg.s%# %q0, %q1" diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index f58d4f5479c..d2e92baeb49 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -775,7 +775,7 @@ (const_string "neon_abs")))] ) -(define_insn "neg2" +(define_insn "neon_neg2" [(set (match_operand:VDQW 0 "s_register_operand" "=w") (neg:VDQW (match_operand:VDQW 1 "s_register_operand" "w")))] "TARGET_NEON" @@ -786,7 +786,7 @@ (const_string "neon_neg")))] ) -(define_insn "2" +(define_insn "neon_2" [(set (match_operand:VH 0 "s_register_operand" "=w") (ABSNEG:VH (match_operand:VH 1 "s_register_operand" "w")))] "TARGET_NEON_FP16INST" @@ -800,7 +800,7 @@ (ABSNEG:VH (match_operand:VH 1 "s_register_operand")))] "TARGET_NEON_FP16INST" { - emit_insn (gen_2 (operands[0], operands[1])); + emit_insn (gen_neon_2 (operands[0], operands[1])); DONE; }) @@ -952,7 +952,7 @@ if (s_register_operand (operands[2], mode)) { rtx neg = gen_reg_rtx (mode); - emit_insn (gen_neg2 (neg, operands[2])); + emit_insn (gen_neon_neg2 (neg, operands[2])); emit_insn (gen_ashl3_signed (operands[0], operands[1], neg)); } else @@ -969,7 +969,7 @@ if (s_register_operand (operands[2], mode)) { rtx neg = gen_reg_rtx (mode); - emit_insn (gen_neg2 (neg, operands[2])); + emit_insn (gen_neon_neg2 (neg, operands[2])); emit_insn (gen_ashl3_unsigned (operands[0], operands[1], neg)); } else @@ -2953,7 +2953,7 @@ (match_operand:VDQW 1 "s_register_operand")] "TARGET_NEON" { - emit_insn (gen_neg2 (operands[0], operands[1])); + emit_insn (gen_neon_neg2 (operands[0], operands[1])); DONE; }) diff --git a/gcc/config/arm/unspecs.md b/gcc/config/arm/unspecs.md index e5816459f12..ef64989600d 100644 --- a/gcc/config/arm/unspecs.md +++ b/gcc/config/arm/unspecs.md @@ -530,7 +530,6 @@ VRNDMQ_F VRNDAQ_F VREV64Q_F - VNEGQ_F VDUPQ_N_F VABSQ_F VREV32Q_F @@ -549,7 +548,6 @@ VREV64Q_S VREV64Q_U VQABSQ_S - VNEGQ_S VDUPQ_N_U VDUPQ_N_S VCLZQ_U diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-common.md index 37ff518fc4e..2d0932b95a1 100644 --- a/gcc/config/arm/vec-common.md +++ b/gcc/config/arm/vec-common.md @@ -199,3 +199,9 @@ (not:VDQ (match_operand:VDQ 1 "s_register_operand")))] "ARM_HAVE__ARITH" ) + +(define_expand "neg2" + [(set (match_operand:VDQWH 0 "s_register_operand" "") + (neg:VDQWH (match_operand:VDQWH 1 "s_register_operand" "")))] + "ARM_HAVE__ARITH" +) diff --git a/gcc/testsuite/gcc.target/arm/simd/mve-vneg.c b/gcc/testsuite/gcc.target/arm/simd/mve-vneg.c new file mode 100644 index 00000000000..afd0d6087bd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/mve-vneg.c @@ -0,0 +1,49 @@ +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O3" } */ + +#include +#include + +#define FUNC(SIGN, TYPE, BITS, NB, OP, NAME) \ + void test_ ## NAME ##_ ## SIGN ## BITS ## x ## NB (TYPE##BITS##_t * __restrict__ dest, TYPE##BITS##_t *a) { \ + int i; \ + for (i=0; i