From 4cc2f2b56e86d6bf98e91d6b855999516cbdd10d Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Mon, 23 Sep 2019 14:17:31 +0100
Subject: [PATCH]

---
 simple_v_extension/bigint_example.mdwn | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/simple_v_extension/bigint_example.mdwn b/simple_v_extension/bigint_example.mdwn
index 8d801db1d..8b153bf31 100644
--- a/simple_v_extension/bigint_example.mdwn
+++ b/simple_v_extension/bigint_example.mdwn
@@ -6,21 +6,21 @@
     VBLK.reg.t4 = {vec}
     VBLK.VL = 8
     {
-     add t4, a0, a1
+     add t4, a0, a1 # vector add of int64
      sub t3, x0, a1 # invert a1
      BLT a0, t3, cont # stores tests in t0
-     ret
+     c.ret
     }
     VBLK.pred.t1 = {inv, t0}
     VBLK.pred.t4 = {t0}
     VBLK.reg.t4 = {vec}
     {
      cont:
-     slli t0, t0, 1 # shifts up carry by 1
-     addi t4, t4, 1 # predicated on t0
+     c.slli t0, 1 # shifts up carry by 1
+     c.addi t4, 1 # predicated on t0
      BLT t4, t1, cont2 # tests into t0
-     ret
+     c.ret
      cont2:
-     j cont
+     c.j cont
     }
 
-- 
2.30.2