From 4cd1d21bfe412e9c6edb8aa74c19ee57370c56c4 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 20 Aug 2019 18:27:16 -0700 Subject: [PATCH] Add (* abc_arrival= *) doc --- README.md | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/README.md b/README.md index fe30348eb..63cefaf26 100644 --- a/README.md +++ b/README.md @@ -414,6 +414,11 @@ Verilog Attributes and non-standard features `abc9` to preserve the integrity of carry-chains. Specifying this attribute onto a bus port will affect only its most significant bit. +- The port attribute ``abc_arrival`` specifies an integer (for output ports + only) to be used as the arrival time of this sequential port. It can be used, + for example, to specify the clk-to-Q delay of a flip-flop for consideration + during techmapping. + Non-standard or SystemVerilog features for formal verification ============================================================== -- 2.30.2