From 4cdb0ddf3a01f9415de8a1c3e73d97e2fcbffbfb Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 13 Apr 2015 13:46:06 +0200 Subject: [PATCH] litescope: pep8 (E265) --- misoclib/tools/litescope/bridge/uart2wb.py | 8 ++++--- misoclib/tools/litescope/core/port.py | 24 ++++++++++++++----- misoclib/tools/litescope/core/storage.py | 20 +++++++++++----- misoclib/tools/litescope/core/trigger.py | 7 +++--- .../litescope/example_designs/test/test_io.py | 8 +++---- .../litescope/example_designs/test/test_la.py | 8 +++---- .../example_designs/test/test_regs.py | 4 ++-- 7 files changed, 51 insertions(+), 28 deletions(-) diff --git a/misoclib/tools/litescope/bridge/uart2wb.py b/misoclib/tools/litescope/bridge/uart2wb.py index ccbf1331..64cd1186 100644 --- a/misoclib/tools/litescope/bridge/uart2wb.py +++ b/misoclib/tools/litescope/bridge/uart2wb.py @@ -22,7 +22,8 @@ class UARTMux(Module): self.shared_pads = UARTPads() self.bridge_pads = UARTPads() - ### + # # # + # Route rx pad: # when sel==0, route it to shared rx and bridge rx # when sel==1, route it only to bridge rx @@ -54,7 +55,9 @@ class LiteScopeUART2WB(Module, AutoCSR): self.wishbone = wishbone.Interface() if share_uart: self._sel = CSRStorage() - ### + + # # # + if share_uart: mux = UARTMux(pads) uart = UARTPHYSerial(mux.bridge_pads, clk_freq, baudrate) @@ -93,7 +96,6 @@ class LiteScopeUART2WB(Module, AutoCSR): ) ] - ### fsm = InsertReset(FSM(reset_state="IDLE")) timeout = Timeout(clk_freq//10) self.submodules += fsm, timeout diff --git a/misoclib/tools/litescope/core/port.py b/misoclib/tools/litescope/core/port.py index 91d702ef..d1c87859 100644 --- a/misoclib/tools/litescope/core/port.py +++ b/misoclib/tools/litescope/core/port.py @@ -9,7 +9,9 @@ class LiteScopeTermUnit(Module): self.trig = Signal(dw) self.mask = Signal(dw) - ### + + # # # + self.comb += [ source.stb.eq(sink.stb), source.hit.eq((sink.data & self.mask) == self.trig), @@ -22,7 +24,9 @@ class LiteScopeTerm(LiteScopeTermUnit, AutoCSR): LiteScopeTermUnit.__init__(self, dw) self._trig = CSRStorage(dw) self._mask = CSRStorage(dw) - ### + + # # # + self.comb += [ self.trig.eq(self._trig.storage), self.mask.eq(self._mask.storage) @@ -37,7 +41,9 @@ class LiteScopeRangeDetectorUnit(Module): self.low = Signal(dw) self.high = Signal(dw) - ### + + # # # + self.comb += [ source.stb.eq(sink.stb), source.hit.eq((sink.data >= self.low) & (sink.data <= self.high)), @@ -50,7 +56,9 @@ class LiteScopeRangeDetector(LiteScopeRangeDetectorUnit, AutoCSR): LiteScopeRangeDetectorUnit.__init__(self, dw) self._low = CSRStorage(dw) self._high = CSRStorage(dw) - ### + + # # # + self.comb += [ self.low.eq(self._low.storage), self.high.eq(self._high.storage) @@ -66,7 +74,9 @@ class LiteScopeEdgeDetectorUnit(Module): self.rising_mask = Signal(dw) self.falling_mask = Signal(dw) self.both_mask = Signal(dw) - ### + + # # # + self.buffer = Buffer(self.sink.description) self.comb += Record.connect(self.sink, self.buffer.sink) @@ -92,7 +102,9 @@ class LiteScopeEdgeDetector(LiteScopeEdgeDetectorUnit, AutoCSR): self._rising = CSRStorage(dw) self._falling = CSRStorage(dw) self._both = CSRStorage(dw) - ### + + # # # + self.comb += [ self.rising.eq(self._rising.storage), self.falling.eq(self._falling.storage), diff --git a/misoclib/tools/litescope/core/storage.py b/misoclib/tools/litescope/core/storage.py index 48bed37a..76c6735b 100644 --- a/misoclib/tools/litescope/core/storage.py +++ b/misoclib/tools/litescope/core/storage.py @@ -7,7 +7,9 @@ class LiteScopeSubSamplerUnit(Module): self.sink = sink = Sink(data_layout(dw)) self.source = source = Source(data_layout(dw)) self.value = Signal(32) - ### + + # # # + self.submodules.counter = Counter(32) done = Signal() self.comb += [ @@ -23,7 +25,9 @@ class LiteScopeSubSampler(LiteScopeSubSamplerUnit, AutoCSR): def __init__(self, dw): LiteScopeSubSamplerUnit.__init__(self, dw) self._value = CSRStorage(32) - ### + + # # # + self.comb += self.value.eq(self._value.storage) @@ -36,7 +40,9 @@ class LiteScopeRunLengthEncoderUnit(Module): self.source = source = Source(data_layout(dw)) self.enable = Signal() - ### + + # # # + self.submodules.buf = buf = Buffer(sink.description) self.comb += Record.connect(sink, buf.d) @@ -82,7 +88,9 @@ class LiteScopeRunLengthEncoder(LiteScopeRunLengthEncoderUnit, AutoCSR): LiteScopeRunLengthEncoderUnit.__init__(self, dw, length) self._enable = CSRStorage() self.external_enable = Signal(reset=1) - ### + + # # # + self.comb += self.enable.eq(self._enable.storage & self.external_enable) @@ -103,7 +111,7 @@ class LiteScopeRecorderUnit(Module): self.source = Source(data_layout(dw)) - ### + # # # fifo = InsertReset(SyncFIFO(data_layout(dw), depth, buffered=True)) self.submodules += fifo @@ -158,7 +166,7 @@ class LiteScopeRecorder(LiteScopeRecorderUnit, AutoCSR): self._source_ack = CSR() self._source_data = CSRStatus(dw) - ### + # # # self.comb += [ self.trigger.eq(self._trigger.re), diff --git a/misoclib/tools/litescope/core/trigger.py b/misoclib/tools/litescope/core/trigger.py index c5aee512..78c5cc5b 100644 --- a/misoclib/tools/litescope/core/trigger.py +++ b/misoclib/tools/litescope/core/trigger.py @@ -15,7 +15,7 @@ class LiteScopeSumUnit(Module, AutoCSR): prog = mem.get_port(write_capable=True) self.specials += mem, lut, prog - ### + # # # # program port self.comb += [ @@ -43,7 +43,9 @@ class LiteScopeSum(LiteScopeSumUnit, AutoCSR): self._prog_we = CSR() self._prog_adr = CSRStorage(ports) self._prog_dat = CSRStorage() - ### + + # # # + self.comb += [ self.prog_we.eq(self._prog_we.re & self._prog_we.r), self.prog_adr.eq(self._prog_adr.storage), @@ -64,7 +66,6 @@ class LiteScopeTrigger(Module, AutoCSR): def do_finalize(self): self.submodules.sum = LiteScopeSum(len(self.ports)) - ### for i, port in enumerate(self.ports): # Note: port's ack is not used and supposed to be always 1 self.comb += [ diff --git a/misoclib/tools/litescope/example_designs/test/test_io.py b/misoclib/tools/litescope/example_designs/test/test_io.py index ec6a9fae..fb853b02 100644 --- a/misoclib/tools/litescope/example_designs/test/test_io.py +++ b/misoclib/tools/litescope/example_designs/test/test_io.py @@ -12,13 +12,13 @@ def led_anim0(io): def led_anim1(io): for j in range(4): - #Led << + # Led << led_data = 1 for i in range(8): io.write(led_data) time.sleep(i*i*0.0020) led_data = (led_data<<1) - #Led >> + # Led >> ledData = 128 for i in range(8): io.write(led_data) @@ -29,9 +29,9 @@ def led_anim1(io): def main(wb): io = LiteScopeIODriver(wb.regs, "io") wb.open() - ### + # # # led_anim0(io) led_anim1(io) print("{:02X}".format(io.read())) - ### + # # # wb.close() diff --git a/misoclib/tools/litescope/example_designs/test/test_la.py b/misoclib/tools/litescope/example_designs/test/test_la.py index 94ba2839..70e2993b 100644 --- a/misoclib/tools/litescope/example_designs/test/test_la.py +++ b/misoclib/tools/litescope/example_designs/test/test_la.py @@ -3,15 +3,15 @@ from misoclib.tools.litescope.host.driver.la import LiteScopeLADriver def main(wb): wb.open() - ### + # # # la = LiteScopeLADriver(wb.regs, "la", debug=True) - #cond = {"cnt0" : 128} # trigger on cnt0 = 128 + # cond = {"cnt0" : 128} # trigger on cnt0 = 128 cond = {} # trigger on cnt0 = 128 la.configure_term(port=0, cond=cond) la.configure_sum("term") la.configure_subsampler(1) - #la.configure_qualifier(1) + # la.configure_qualifier(1) la.configure_rle(1) la.run(offset=128, length=256) @@ -23,5 +23,5 @@ def main(wb): la.save("dump.csv") la.save("dump.py") la.save("dump.sr") - ### + # # # wb.close() diff --git a/misoclib/tools/litescope/example_designs/test/test_regs.py b/misoclib/tools/litescope/example_designs/test/test_regs.py index 1f29e49b..21deed9d 100644 --- a/misoclib/tools/litescope/example_designs/test/test_regs.py +++ b/misoclib/tools/litescope/example_designs/test/test_regs.py @@ -1,9 +1,9 @@ def main(wb): wb.open() regs = wb.regs - ### + # # # print("sysid : 0x{:04x}".format(regs.identifier_sysid.read())) print("revision : 0x{:04x}".format(regs.identifier_revision.read())) print("frequency : {}MHz".format(int(regs.identifier_frequency.read()/1000000))) - ### + # # # wb.close() -- 2.30.2