From 4cdba00e25d892b90c0ee48716c17dec60e472db Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 31 Dec 2019 15:24:02 -0800 Subject: [PATCH] FDCE ports to be alphabetical --- techlibs/xilinx/cells_sim.v | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 4d20e1d2c..982ccad72 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -405,10 +405,10 @@ module FDCE ( (* invertible_pin = "IS_C_INVERTED" *) input C, input CE, - (* invertible_pin = "IS_D_INVERTED" *) - input D, (* invertible_pin = "IS_CLR_INVERTED" *) - input CLR + input CLR, + (* invertible_pin = "IS_D_INVERTED" *) + input D ); parameter [0:0] INIT = 1'b0; parameter [0:0] IS_C_INVERTED = 1'b0; -- 2.30.2