From 4d0a023751b086e7f11dc4529042104a9bd8cb1b Mon Sep 17 00:00:00 2001 From: Charles Baylis Date: Wed, 22 Jul 2015 10:44:16 +0000 Subject: [PATCH] re PR target/63870 ([Aarch64] [ARM] Errors in use of NEON intrinsics are reported incorrectly) gcc/ChangeLog: 2015-07-22 Charles Baylis PR target/63870 * config/aarch64/aarch64-builtins.c (enum aarch64_type_qualifiers): Add qualifier_struct_load_store_lane_index. (aarch64_types_loadstruct_lane_qualifiers): Use qualifier_struct_load_store_lane_index for lane index argument for last argument. (aarch64_types_storestruct_lane_qualifiers): Ditto. (builtin_simd_arg): Add SIMD_ARG_STRUCT_LOAD_STORE_LANE_INDEX. (aarch64_simd_expand_args): Add new argument describing mode of builtin. Check lane bounds for arguments with SIMD_ARG_STRUCT_LOAD_STORE_LANE_INDEX. (aarch64_simd_expand_builtin): Emit error for incorrect lane indices if marked with SIMD_ARG_STRUCT_LOAD_STORE_LANE_INDEX. (aarch64_simd_expand_builtin): Handle arguments with qualifier_struct_load_store_lane_index. Pass machine mode of builtin to aarch64_simd_expand_args. * config/aarch64/aarch64-simd-builtins.def: Declare ld[234]_lane and vst[234]_lane with BUILTIN_VALLDIF. * config/aarch64/aarch64-simd.md: (aarch64_vec_load_lanesoi_lane): Use VALLDIF iterator. Perform endianness reversal on lane index. (aarch64_vec_load_lanesci_lane): Ditto. (aarch64_vec_load_lanesxi_lane): Ditto. (vec_store_lanesoi_lane): Use VALLDIF iterator. (vec_store_lanesci_lane): Ditto. (vec_store_lanesxi_lane): Ditto. (aarch64_ld2_lane): Use VALLDIF iterator. Remove endianness reversal of lane index. (aarch64_ld3_lane): Ditto. (aarch64_ld4_lane): Ditto. (aarch64_st2_lane): Ditto. (aarch64_st3_lane): Ditto. (aarch64_st4_lane): Ditto. * config/aarch64/arm_neon.h (__LD2_LANE_FUNC): Rename mode parameter to qmode. Add new mode parameter. Update uses. (__LD3_LANE_FUNC): Ditto. (__LD4_LANE_FUNC): Ditto. (__ST2_LANE_FUNC): Ditto. (__ST3_LANE_FUNC): Ditto. (__ST4_LANE_FUNC): Ditto. gcc/testsuite/ChangeLog: 2015-07-22 Charles Baylis * gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f32_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f64_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld2_lane_p8_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s16_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s32_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s64_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s8_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u16_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u32_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u64_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u8_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f32_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f64_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_p8_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s16_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s32_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s64_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s8_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u16_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u32_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u64_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u8_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f32_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f64_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld3_lane_p8_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s16_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s32_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s64_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s8_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u16_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u32_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u64_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u8_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f32_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f64_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_p8_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s16_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s32_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s64_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s8_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u16_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u32_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u64_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u8_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f32_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f64_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld4_lane_p8_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s16_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s32_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s64_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s8_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u16_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u32_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u64_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u8_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f32_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f64_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_p8_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s16_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s32_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s64_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s8_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u16_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u32_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u64_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u8_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f32_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f64_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst2_lane_p8_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s16_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s32_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s64_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s8_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u16_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u32_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u64_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u8_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f32_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f64_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_p8_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s16_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s32_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s64_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s8_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u16_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u32_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u64_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u8_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f32_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f64_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst3_lane_p8_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s16_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s32_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s64_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s8_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u16_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u32_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u64_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u8_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f32_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f64_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_p8_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s16_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s32_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s64_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s8_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u16_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u32_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u64_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u8_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f32_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f64_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst4_lane_p8_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s16_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s32_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s64_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s8_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u16_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u32_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u64_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u8_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f32_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f64_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_p8_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s16_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s32_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s64_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s8_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u16_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u32_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u64_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u8_indices_1.c: New test. From-SVN: r226059 --- gcc/ChangeLog | 43 +++ gcc/config/aarch64/aarch64-builtins.c | 30 +- gcc/config/aarch64/aarch64-simd-builtins.def | 12 +- gcc/config/aarch64/aarch64-simd.md | 72 +++-- gcc/config/aarch64/arm_neon.h | 276 ++++++++++-------- gcc/testsuite/ChangeLog | 267 +++++++++++++++++ .../vld2_lane_f32_indices_1.c | 16 + .../vld2_lane_f64_indices_1.c | 17 ++ .../vld2_lane_p8_indices_1.c | 16 + .../vld2_lane_s16_indices_1.c | 16 + .../vld2_lane_s32_indices_1.c | 16 + .../vld2_lane_s64_indices_1.c | 17 ++ .../vld2_lane_s8_indices_1.c | 16 + .../vld2_lane_u16_indices_1.c | 16 + .../vld2_lane_u32_indices_1.c | 16 + .../vld2_lane_u64_indices_1.c | 17 ++ .../vld2_lane_u8_indices_1.c | 16 + .../vld2q_lane_f32_indices_1.c | 16 + .../vld2q_lane_f64_indices_1.c | 17 ++ .../vld2q_lane_p8_indices_1.c | 17 ++ .../vld2q_lane_s16_indices_1.c | 16 + .../vld2q_lane_s32_indices_1.c | 16 + .../vld2q_lane_s64_indices_1.c | 17 ++ .../vld2q_lane_s8_indices_1.c | 17 ++ .../vld2q_lane_u16_indices_1.c | 16 + .../vld2q_lane_u32_indices_1.c | 16 + .../vld2q_lane_u64_indices_1.c | 17 ++ .../vld2q_lane_u8_indices_1.c | 17 ++ .../vld3_lane_f32_indices_1.c | 16 + .../vld3_lane_f64_indices_1.c | 17 ++ .../vld3_lane_p8_indices_1.c | 16 + .../vld3_lane_s16_indices_1.c | 16 + .../vld3_lane_s32_indices_1.c | 16 + .../vld3_lane_s64_indices_1.c | 17 ++ .../vld3_lane_s8_indices_1.c | 16 + .../vld3_lane_u16_indices_1.c | 16 + .../vld3_lane_u32_indices_1.c | 16 + .../vld3_lane_u64_indices_1.c | 17 ++ .../vld3_lane_u8_indices_1.c | 16 + .../vld3q_lane_f32_indices_1.c | 16 + .../vld3q_lane_f64_indices_1.c | 17 ++ .../vld3q_lane_p8_indices_1.c | 17 ++ .../vld3q_lane_s16_indices_1.c | 16 + .../vld3q_lane_s32_indices_1.c | 16 + .../vld3q_lane_s64_indices_1.c | 17 ++ .../vld3q_lane_s8_indices_1.c | 17 ++ .../vld3q_lane_u16_indices_1.c | 16 + .../vld3q_lane_u32_indices_1.c | 16 + .../vld3q_lane_u64_indices_1.c | 17 ++ .../vld3q_lane_u8_indices_1.c | 17 ++ .../vld4_lane_f32_indices_1.c | 16 + .../vld4_lane_f64_indices_1.c | 17 ++ .../vld4_lane_p8_indices_1.c | 16 + .../vld4_lane_s16_indices_1.c | 16 + .../vld4_lane_s32_indices_1.c | 16 + .../vld4_lane_s64_indices_1.c | 17 ++ .../vld4_lane_s8_indices_1.c | 16 + .../vld4_lane_u16_indices_1.c | 16 + .../vld4_lane_u32_indices_1.c | 16 + .../vld4_lane_u64_indices_1.c | 17 ++ .../vld4_lane_u8_indices_1.c | 16 + .../vld4q_lane_f32_indices_1.c | 16 + .../vld4q_lane_f64_indices_1.c | 17 ++ .../vld4q_lane_p8_indices_1.c | 17 ++ .../vld4q_lane_s16_indices_1.c | 16 + .../vld4q_lane_s32_indices_1.c | 16 + .../vld4q_lane_s64_indices_1.c | 17 ++ .../vld4q_lane_s8_indices_1.c | 17 ++ .../vld4q_lane_u16_indices_1.c | 16 + .../vld4q_lane_u32_indices_1.c | 16 + .../vld4q_lane_u64_indices_1.c | 17 ++ .../vld4q_lane_u8_indices_1.c | 17 ++ .../vst2_lane_f32_indices_1.c | 15 + .../vst2_lane_f64_indices_1.c | 16 + .../vst2_lane_p8_indices_1.c | 15 + .../vst2_lane_s16_indices_1.c | 15 + .../vst2_lane_s32_indices_1.c | 15 + .../vst2_lane_s64_indices_1.c | 16 + .../vst2_lane_s8_indices_1.c | 15 + .../vst2_lane_u16_indices_1.c | 15 + .../vst2_lane_u32_indices_1.c | 15 + .../vst2_lane_u64_indices_1.c | 16 + .../vst2_lane_u8_indices_1.c | 15 + .../vst2q_lane_f32_indices_1.c | 15 + .../vst2q_lane_f64_indices_1.c | 16 + .../vst2q_lane_p8_indices_1.c | 16 + .../vst2q_lane_s16_indices_1.c | 15 + .../vst2q_lane_s32_indices_1.c | 15 + .../vst2q_lane_s64_indices_1.c | 16 + .../vst2q_lane_s8_indices_1.c | 16 + .../vst2q_lane_u16_indices_1.c | 15 + .../vst2q_lane_u32_indices_1.c | 15 + .../vst2q_lane_u64_indices_1.c | 16 + .../vst2q_lane_u8_indices_1.c | 16 + .../vst3_lane_f32_indices_1.c | 15 + .../vst3_lane_f64_indices_1.c | 16 + .../vst3_lane_p8_indices_1.c | 15 + .../vst3_lane_s16_indices_1.c | 15 + .../vst3_lane_s32_indices_1.c | 15 + .../vst3_lane_s64_indices_1.c | 16 + .../vst3_lane_s8_indices_1.c | 15 + .../vst3_lane_u16_indices_1.c | 15 + .../vst3_lane_u32_indices_1.c | 15 + .../vst3_lane_u64_indices_1.c | 16 + .../vst3_lane_u8_indices_1.c | 15 + .../vst3q_lane_f32_indices_1.c | 15 + .../vst3q_lane_f64_indices_1.c | 16 + .../vst3q_lane_p8_indices_1.c | 16 + .../vst3q_lane_s16_indices_1.c | 15 + .../vst3q_lane_s32_indices_1.c | 15 + .../vst3q_lane_s64_indices_1.c | 16 + .../vst3q_lane_s8_indices_1.c | 16 + .../vst3q_lane_u16_indices_1.c | 15 + .../vst3q_lane_u32_indices_1.c | 15 + .../vst3q_lane_u64_indices_1.c | 16 + .../vst3q_lane_u8_indices_1.c | 16 + .../vst4_lane_f32_indices_1.c | 15 + .../vst4_lane_f64_indices_1.c | 16 + .../vst4_lane_p8_indices_1.c | 15 + .../vst4_lane_s16_indices_1.c | 15 + .../vst4_lane_s32_indices_1.c | 15 + .../vst4_lane_s64_indices_1.c | 16 + .../vst4_lane_s8_indices_1.c | 15 + .../vst4_lane_u16_indices_1.c | 15 + .../vst4_lane_u32_indices_1.c | 15 + .../vst4_lane_u64_indices_1.c | 16 + .../vst4_lane_u8_indices_1.c | 15 + .../vst4q_lane_f32_indices_1.c | 15 + .../vst4q_lane_f64_indices_1.c | 16 + .../vst4q_lane_p8_indices_1.c | 16 + .../vst4q_lane_s16_indices_1.c | 15 + .../vst4q_lane_s32_indices_1.c | 15 + .../vst4q_lane_s64_indices_1.c | 16 + .../vst4q_lane_s8_indices_1.c | 16 + .../vst4q_lane_u16_indices_1.c | 15 + .../vst4q_lane_u32_indices_1.c | 15 + .../vst4q_lane_u64_indices_1.c | 16 + .../vst4q_lane_u8_indices_1.c | 16 + 138 files changed, 2621 insertions(+), 179 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f32_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f64_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_p8_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s16_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s32_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s64_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s8_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u16_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u32_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u64_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u8_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f32_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f64_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_p8_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s16_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s32_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s64_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s8_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u16_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u32_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u64_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u8_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f32_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f64_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_p8_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s16_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s32_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s64_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s8_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u16_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u32_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u64_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u8_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f32_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f64_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_p8_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s16_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s32_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s64_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s8_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u16_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u32_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u64_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u8_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f32_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f64_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_p8_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s16_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s32_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s64_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s8_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u16_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u32_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u64_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u8_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f32_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f64_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_p8_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s16_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s32_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s64_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s8_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u16_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u32_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u64_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u8_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f32_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f64_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_p8_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s16_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s32_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s64_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s8_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u16_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u32_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u64_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u8_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f32_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f64_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_p8_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s16_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s32_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s64_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s8_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u16_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u32_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u64_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u8_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f32_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f64_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_p8_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s16_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s32_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s64_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s8_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u16_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u32_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u64_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u8_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f32_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f64_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_p8_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s16_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s32_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s64_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s8_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u16_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u32_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u64_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u8_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f32_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f64_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_p8_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s16_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s32_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s64_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s8_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u16_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u32_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u64_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u8_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f32_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f64_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_p8_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s16_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s32_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s64_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s8_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u16_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u32_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u64_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u8_indices_1.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 7e2c0b0bf5a..079432fd156 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,46 @@ +2015-07-22 Charles Baylis + + PR target/63870 + * config/aarch64/aarch64-builtins.c (enum aarch64_type_qualifiers): + Add qualifier_struct_load_store_lane_index. + (aarch64_types_loadstruct_lane_qualifiers): Use + qualifier_struct_load_store_lane_index for lane index argument for + last argument. + (aarch64_types_storestruct_lane_qualifiers): Ditto. + (builtin_simd_arg): Add SIMD_ARG_STRUCT_LOAD_STORE_LANE_INDEX. + (aarch64_simd_expand_args): Add new argument describing mode of + builtin. Check lane bounds for arguments with + SIMD_ARG_STRUCT_LOAD_STORE_LANE_INDEX. + (aarch64_simd_expand_builtin): Emit error for incorrect lane indices + if marked with SIMD_ARG_STRUCT_LOAD_STORE_LANE_INDEX. + (aarch64_simd_expand_builtin): Handle arguments with + qualifier_struct_load_store_lane_index. Pass machine mode of builtin to + aarch64_simd_expand_args. + * config/aarch64/aarch64-simd-builtins.def: Declare ld[234]_lane and + vst[234]_lane with BUILTIN_VALLDIF. + * config/aarch64/aarch64-simd.md: + (aarch64_vec_load_lanesoi_lane): Use VALLDIF iterator. Perform + endianness reversal on lane index. + (aarch64_vec_load_lanesci_lane): Ditto. + (aarch64_vec_load_lanesxi_lane): Ditto. + (vec_store_lanesoi_lane): Use VALLDIF iterator. + (vec_store_lanesci_lane): Ditto. + (vec_store_lanesxi_lane): Ditto. + (aarch64_ld2_lane): Use VALLDIF iterator. Remove endianness + reversal of lane index. + (aarch64_ld3_lane): Ditto. + (aarch64_ld4_lane): Ditto. + (aarch64_st2_lane): Ditto. + (aarch64_st3_lane): Ditto. + (aarch64_st4_lane): Ditto. + * config/aarch64/arm_neon.h (__LD2_LANE_FUNC): Rename mode parameter + to qmode. Add new mode parameter. Update uses. + (__LD3_LANE_FUNC): Ditto. + (__LD4_LANE_FUNC): Ditto. + (__ST2_LANE_FUNC): Ditto. + (__ST3_LANE_FUNC): Ditto. + (__ST4_LANE_FUNC): Ditto. + 2015-07-22 Jonathan Wakely * doc/invoke.texi (Language Independent Options): Rename node to diff --git a/gcc/config/aarch64/aarch64-builtins.c b/gcc/config/aarch64/aarch64-builtins.c index 294bf9d906b..4b783294061 100644 --- a/gcc/config/aarch64/aarch64-builtins.c +++ b/gcc/config/aarch64/aarch64-builtins.c @@ -114,7 +114,9 @@ enum aarch64_type_qualifiers /* Polynomial types. */ qualifier_poly = 0x100, /* Lane indices - must be in range, and flipped for bigendian. */ - qualifier_lane_index = 0x200 + qualifier_lane_index = 0x200, + /* Lane indices for single lane structure loads and stores. */ + qualifier_struct_load_store_lane_index = 0x400 }; typedef struct @@ -216,7 +218,7 @@ aarch64_types_load1_qualifiers[SIMD_MAX_BUILTIN_ARGS] static enum aarch64_type_qualifiers aarch64_types_loadstruct_lane_qualifiers[SIMD_MAX_BUILTIN_ARGS] = { qualifier_none, qualifier_const_pointer_map_mode, - qualifier_none, qualifier_none }; + qualifier_none, qualifier_struct_load_store_lane_index }; #define TYPES_LOADSTRUCT_LANE (aarch64_types_loadstruct_lane_qualifiers) static enum aarch64_type_qualifiers @@ -248,7 +250,7 @@ aarch64_types_store1_qualifiers[SIMD_MAX_BUILTIN_ARGS] static enum aarch64_type_qualifiers aarch64_types_storestruct_lane_qualifiers[SIMD_MAX_BUILTIN_ARGS] = { qualifier_void, qualifier_pointer_map_mode, - qualifier_none, qualifier_none }; + qualifier_none, qualifier_struct_load_store_lane_index }; #define TYPES_STORESTRUCT_LANE (aarch64_types_storestruct_lane_qualifiers) #define CF0(N, X) CODE_FOR_aarch64_##N##X @@ -864,12 +866,14 @@ typedef enum SIMD_ARG_COPY_TO_REG, SIMD_ARG_CONSTANT, SIMD_ARG_LANE_INDEX, + SIMD_ARG_STRUCT_LOAD_STORE_LANE_INDEX, SIMD_ARG_STOP } builtin_simd_arg; static rtx aarch64_simd_expand_args (rtx target, int icode, int have_retval, - tree exp, builtin_simd_arg *args) + tree exp, builtin_simd_arg *args, + enum machine_mode builtin_mode) { rtx pat; rtx op[SIMD_MAX_BUILTIN_ARGS + 1]; /* First element for result operand. */ @@ -908,6 +912,19 @@ aarch64_simd_expand_args (rtx target, int icode, int have_retval, op[opc] = copy_to_mode_reg (mode, op[opc]); break; + case SIMD_ARG_STRUCT_LOAD_STORE_LANE_INDEX: + gcc_assert (opc > 1); + if (CONST_INT_P (op[opc])) + { + aarch64_simd_lane_bounds (op[opc], 0, + GET_MODE_NUNITS (builtin_mode), + exp); + /* Keep to GCC-vector-extension lane indices in the RTL. */ + op[opc] = + GEN_INT (ENDIAN_LANE_N (builtin_mode, INTVAL (op[opc]))); + } + goto constant_arg; + case SIMD_ARG_LANE_INDEX: /* Must be a previous operand into which this is an index. */ gcc_assert (opc > 0); @@ -922,6 +939,7 @@ aarch64_simd_expand_args (rtx target, int icode, int have_retval, /* Fall through - if the lane index isn't a constant then the next case will error. */ case SIMD_ARG_CONSTANT: +constant_arg: if (!(*insn_data[icode].operand[opc].predicate) (op[opc], mode)) { @@ -1030,6 +1048,8 @@ aarch64_simd_expand_builtin (int fcode, tree exp, rtx target) if (d->qualifiers[qualifiers_k] & qualifier_lane_index) args[k] = SIMD_ARG_LANE_INDEX; + else if (d->qualifiers[qualifiers_k] & qualifier_struct_load_store_lane_index) + args[k] = SIMD_ARG_STRUCT_LOAD_STORE_LANE_INDEX; else if (d->qualifiers[qualifiers_k] & qualifier_immediate) args[k] = SIMD_ARG_CONSTANT; else if (d->qualifiers[qualifiers_k] & qualifier_maybe_immediate) @@ -1053,7 +1073,7 @@ aarch64_simd_expand_builtin (int fcode, tree exp, rtx target) /* The interface to aarch64_simd_expand_args expects a 0 if the function is void, and a 1 if it is not. */ return aarch64_simd_expand_args - (target, icode, !is_void, exp, &args[1]); + (target, icode, !is_void, exp, &args[1], d->mode); } rtx diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def index dd2bc47ae1e..d0f298a1f07 100644 --- a/gcc/config/aarch64/aarch64-simd-builtins.def +++ b/gcc/config/aarch64/aarch64-simd-builtins.def @@ -88,9 +88,9 @@ BUILTIN_VALLDIF (LOADSTRUCT, ld3r, 0) BUILTIN_VALLDIF (LOADSTRUCT, ld4r, 0) /* Implemented by aarch64_ld_lane. */ - BUILTIN_VQ (LOADSTRUCT_LANE, ld2_lane, 0) - BUILTIN_VQ (LOADSTRUCT_LANE, ld3_lane, 0) - BUILTIN_VQ (LOADSTRUCT_LANE, ld4_lane, 0) + BUILTIN_VALLDIF (LOADSTRUCT_LANE, ld2_lane, 0) + BUILTIN_VALLDIF (LOADSTRUCT_LANE, ld3_lane, 0) + BUILTIN_VALLDIF (LOADSTRUCT_LANE, ld4_lane, 0) /* Implemented by aarch64_st. */ BUILTIN_VDC (STORESTRUCT, st2, 0) BUILTIN_VDC (STORESTRUCT, st3, 0) @@ -100,9 +100,9 @@ BUILTIN_VQ (STORESTRUCT, st3, 0) BUILTIN_VQ (STORESTRUCT, st4, 0) - BUILTIN_VQ (STORESTRUCT_LANE, st2_lane, 0) - BUILTIN_VQ (STORESTRUCT_LANE, st3_lane, 0) - BUILTIN_VQ (STORESTRUCT_LANE, st4_lane, 0) + BUILTIN_VALLDIF (STORESTRUCT_LANE, st2_lane, 0) + BUILTIN_VALLDIF (STORESTRUCT_LANE, st3_lane, 0) + BUILTIN_VALLDIF (STORESTRUCT_LANE, st4_lane, 0) BUILTIN_VQW (BINOP, saddl2, 0) BUILTIN_VQW (BINOP, uaddl2, 0) diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index b90f93841f8..d5da35ad769 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -3919,10 +3919,13 @@ (unspec:OI [(match_operand: 1 "aarch64_simd_struct_operand" "Utv") (match_operand:OI 2 "register_operand" "0") (match_operand:SI 3 "immediate_operand" "i") - (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY) ] + (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY) ] UNSPEC_LD2_LANE))] "TARGET_SIMD" - "ld2\\t{%S0. - %T0.}[%3], %1" + { + operands[3] = GEN_INT (ENDIAN_LANE_N (mode, INTVAL (operands[3]))); + return "ld2\\t{%S0. - %T0.}[%3], %1"; + } [(set_attr "type" "neon_load2_one_lane")] ) @@ -3959,9 +3962,9 @@ (define_insn "vec_store_lanesoi_lane" [(set (match_operand: 0 "aarch64_simd_struct_operand" "=Utv") (unspec: [(match_operand:OI 1 "register_operand" "w") - (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY) + (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY) (match_operand:SI 2 "immediate_operand" "i")] - UNSPEC_ST2_LANE))] + UNSPEC_ST2_LANE))] "TARGET_SIMD" { operands[2] = GEN_INT (ENDIAN_LANE_N (mode, INTVAL (operands[2]))); @@ -4014,10 +4017,13 @@ (unspec:CI [(match_operand: 1 "aarch64_simd_struct_operand" "Utv") (match_operand:CI 2 "register_operand" "0") (match_operand:SI 3 "immediate_operand" "i") - (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] UNSPEC_LD3_LANE))] "TARGET_SIMD" - "ld3\\t{%S0. - %U0.}[%3], %1" +{ + operands[3] = GEN_INT (ENDIAN_LANE_N (mode, INTVAL (operands[3]))); + return "ld3\\t{%S0. - %U0.}[%3], %1"; +} [(set_attr "type" "neon_load3_one_lane")] ) @@ -4054,9 +4060,9 @@ (define_insn "vec_store_lanesci_lane" [(set (match_operand: 0 "aarch64_simd_struct_operand" "=Utv") (unspec: [(match_operand:CI 1 "register_operand" "w") - (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY) + (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY) (match_operand:SI 2 "immediate_operand" "i")] - UNSPEC_ST3_LANE))] + UNSPEC_ST3_LANE))] "TARGET_SIMD" { operands[2] = GEN_INT (ENDIAN_LANE_N (mode, INTVAL (operands[2]))); @@ -4109,10 +4115,13 @@ (unspec:XI [(match_operand: 1 "aarch64_simd_struct_operand" "Utv") (match_operand:XI 2 "register_operand" "0") (match_operand:SI 3 "immediate_operand" "i") - (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] UNSPEC_LD4_LANE))] "TARGET_SIMD" - "ld4\\t{%S0. - %V0.}[%3], %1" +{ + operands[3] = GEN_INT (ENDIAN_LANE_N (mode, INTVAL (operands[3]))); + return "ld4\\t{%S0. - %V0.}[%3], %1"; +} [(set_attr "type" "neon_load4_one_lane")] ) @@ -4149,9 +4158,9 @@ (define_insn "vec_store_lanesxi_lane" [(set (match_operand: 0 "aarch64_simd_struct_operand" "=Utv") (unspec: [(match_operand:XI 1 "register_operand" "w") - (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY) + (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY) (match_operand:SI 2 "immediate_operand" "i")] - UNSPEC_ST4_LANE))] + UNSPEC_ST4_LANE))] "TARGET_SIMD" { operands[2] = GEN_INT (ENDIAN_LANE_N (mode, INTVAL (operands[2]))); @@ -4566,14 +4575,12 @@ (match_operand:DI 1 "register_operand" "w") (match_operand:OI 2 "register_operand" "0") (match_operand:SI 3 "immediate_operand" "i") - (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] "TARGET_SIMD" { machine_mode mode = mode; rtx mem = gen_rtx_MEM (mode, operands[1]); - aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (mode), - NULL); emit_insn (gen_aarch64_vec_load_lanesoi_lane (operands[0], mem, operands[2], @@ -4586,14 +4593,12 @@ (match_operand:DI 1 "register_operand" "w") (match_operand:CI 2 "register_operand" "0") (match_operand:SI 3 "immediate_operand" "i") - (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] "TARGET_SIMD" { machine_mode mode = mode; rtx mem = gen_rtx_MEM (mode, operands[1]); - aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (mode), - NULL); emit_insn (gen_aarch64_vec_load_lanesci_lane (operands[0], mem, operands[2], @@ -4606,14 +4611,12 @@ (match_operand:DI 1 "register_operand" "w") (match_operand:XI 2 "register_operand" "0") (match_operand:SI 3 "immediate_operand" "i") - (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] "TARGET_SIMD" { machine_mode mode = mode; rtx mem = gen_rtx_MEM (mode, operands[1]); - aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (mode), - NULL); emit_insn (gen_aarch64_vec_load_lanesxi_lane (operands[0], mem, operands[2], @@ -4850,54 +4853,45 @@ DONE; }) -(define_expand "aarch64_st2_lane" +(define_expand "aarch64_st2_lane" [(match_operand:DI 0 "register_operand" "r") (match_operand:OI 1 "register_operand" "w") - (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY) + (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY) (match_operand:SI 2 "immediate_operand")] "TARGET_SIMD" { machine_mode mode = mode; rtx mem = gen_rtx_MEM (mode, operands[0]); - operands[2] = GEN_INT (ENDIAN_LANE_N (mode, INTVAL (operands[2]))); - emit_insn (gen_vec_store_lanesoi_lane (mem, - operands[1], - operands[2])); + emit_insn (gen_vec_store_lanesoi_lane (mem, operands[1], operands[2])); DONE; }) -(define_expand "aarch64_st3_lane" +(define_expand "aarch64_st3_lane" [(match_operand:DI 0 "register_operand" "r") (match_operand:CI 1 "register_operand" "w") - (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY) + (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY) (match_operand:SI 2 "immediate_operand")] "TARGET_SIMD" { machine_mode mode = mode; rtx mem = gen_rtx_MEM (mode, operands[0]); - operands[2] = GEN_INT (ENDIAN_LANE_N (mode, INTVAL (operands[2]))); - emit_insn (gen_vec_store_lanesci_lane (mem, - operands[1], - operands[2])); + emit_insn (gen_vec_store_lanesci_lane (mem, operands[1], operands[2])); DONE; }) -(define_expand "aarch64_st4_lane" +(define_expand "aarch64_st4_lane" [(match_operand:DI 0 "register_operand" "r") (match_operand:XI 1 "register_operand" "w") - (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY) + (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY) (match_operand:SI 2 "immediate_operand")] "TARGET_SIMD" { machine_mode mode = mode; rtx mem = gen_rtx_MEM (mode, operands[0]); - operands[2] = GEN_INT (ENDIAN_LANE_N (mode, INTVAL (operands[2]))); - emit_insn (gen_vec_store_lanesxi_lane (mem, - operands[1], - operands[2])); + emit_insn (gen_vec_store_lanesxi_lane (mem, operands[1], operands[2])); DONE; }) diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h index 114994e48b7..fce557779c2 100644 --- a/gcc/config/aarch64/arm_neon.h +++ b/gcc/config/aarch64/arm_neon.h @@ -9950,8 +9950,8 @@ __STRUCTN (float, 64, 4) #undef __STRUCTN -#define __ST2_LANE_FUNC(intype, largetype, ptrtype, \ - mode, ptr_mode, funcsuffix, signedtype) \ +#define __ST2_LANE_FUNC(intype, largetype, ptrtype, mode, \ + qmode, ptr_mode, funcsuffix, signedtype) \ __extension__ static __inline void \ __attribute__ ((__always_inline__)) \ vst2_lane_ ## funcsuffix (ptrtype *__ptr, \ @@ -9965,31 +9965,37 @@ vst2_lane_ ## funcsuffix (ptrtype *__ptr, \ __temp.val[1] \ = vcombine_##funcsuffix (__b.val[1], \ vcreate_##funcsuffix (__AARCH64_UINT64_C (0))); \ - __o = __builtin_aarch64_set_qregoi##mode (__o, \ - (signedtype) __temp.val[0], 0); \ - __o = __builtin_aarch64_set_qregoi##mode (__o, \ - (signedtype) __temp.val[1], 1); \ + __o = __builtin_aarch64_set_qregoi##qmode (__o, \ + (signedtype) __temp.val[0], 0); \ + __o = __builtin_aarch64_set_qregoi##qmode (__o, \ + (signedtype) __temp.val[1], 1); \ __builtin_aarch64_st2_lane##mode ((__builtin_aarch64_simd_ ## ptr_mode *) \ __ptr, __o, __c); \ } -__ST2_LANE_FUNC (float32x2x2_t, float32x4x2_t, float32_t, v4sf, sf, f32, +__ST2_LANE_FUNC (float32x2x2_t, float32x4x2_t, float32_t, v2sf, v4sf, sf, f32, float32x4_t) -__ST2_LANE_FUNC (float64x1x2_t, float64x2x2_t, float64_t, v2df, df, f64, +__ST2_LANE_FUNC (float64x1x2_t, float64x2x2_t, float64_t, df, v2df, df, f64, float64x2_t) -__ST2_LANE_FUNC (poly8x8x2_t, poly8x16x2_t, poly8_t, v16qi, qi, p8, int8x16_t) -__ST2_LANE_FUNC (poly16x4x2_t, poly16x8x2_t, poly16_t, v8hi, hi, p16, +__ST2_LANE_FUNC (poly8x8x2_t, poly8x16x2_t, poly8_t, v8qi, v16qi, qi, p8, + int8x16_t) +__ST2_LANE_FUNC (poly16x4x2_t, poly16x8x2_t, poly16_t, v4hi, v8hi, hi, p16, int16x8_t) -__ST2_LANE_FUNC (int8x8x2_t, int8x16x2_t, int8_t, v16qi, qi, s8, int8x16_t) -__ST2_LANE_FUNC (int16x4x2_t, int16x8x2_t, int16_t, v8hi, hi, s16, int16x8_t) -__ST2_LANE_FUNC (int32x2x2_t, int32x4x2_t, int32_t, v4si, si, s32, int32x4_t) -__ST2_LANE_FUNC (int64x1x2_t, int64x2x2_t, int64_t, v2di, di, s64, int64x2_t) -__ST2_LANE_FUNC (uint8x8x2_t, uint8x16x2_t, uint8_t, v16qi, qi, u8, int8x16_t) -__ST2_LANE_FUNC (uint16x4x2_t, uint16x8x2_t, uint16_t, v8hi, hi, u16, +__ST2_LANE_FUNC (int8x8x2_t, int8x16x2_t, int8_t, v8qi, v16qi, qi, s8, + int8x16_t) +__ST2_LANE_FUNC (int16x4x2_t, int16x8x2_t, int16_t, v4hi, v8hi, hi, s16, int16x8_t) -__ST2_LANE_FUNC (uint32x2x2_t, uint32x4x2_t, uint32_t, v4si, si, u32, +__ST2_LANE_FUNC (int32x2x2_t, int32x4x2_t, int32_t, v2si, v4si, si, s32, int32x4_t) -__ST2_LANE_FUNC (uint64x1x2_t, uint64x2x2_t, uint64_t, v2di, di, u64, +__ST2_LANE_FUNC (int64x1x2_t, int64x2x2_t, int64_t, di, v2di, di, s64, + int64x2_t) +__ST2_LANE_FUNC (uint8x8x2_t, uint8x16x2_t, uint8_t, v8qi, v16qi, qi, u8, + int8x16_t) +__ST2_LANE_FUNC (uint16x4x2_t, uint16x8x2_t, uint16_t, v4hi, v8hi, hi, u16, + int16x8_t) +__ST2_LANE_FUNC (uint32x2x2_t, uint32x4x2_t, uint32_t, v2si, v4si, si, u32, + int32x4_t) +__ST2_LANE_FUNC (uint64x1x2_t, uint64x2x2_t, uint64_t, di, v2di, di, u64, int64x2_t) #undef __ST2_LANE_FUNC @@ -10018,8 +10024,8 @@ __ST2_LANE_FUNC (uint16x8x2_t, uint16_t, v8hi, hi, u16) __ST2_LANE_FUNC (uint32x4x2_t, uint32_t, v4si, si, u32) __ST2_LANE_FUNC (uint64x2x2_t, uint64_t, v2di, di, u64) -#define __ST3_LANE_FUNC(intype, largetype, ptrtype, \ - mode, ptr_mode, funcsuffix, signedtype) \ +#define __ST3_LANE_FUNC(intype, largetype, ptrtype, mode, \ + qmode, ptr_mode, funcsuffix, signedtype) \ __extension__ static __inline void \ __attribute__ ((__always_inline__)) \ vst3_lane_ ## funcsuffix (ptrtype *__ptr, \ @@ -10036,33 +10042,39 @@ vst3_lane_ ## funcsuffix (ptrtype *__ptr, \ __temp.val[2] \ = vcombine_##funcsuffix (__b.val[2], \ vcreate_##funcsuffix (__AARCH64_UINT64_C (0))); \ - __o = __builtin_aarch64_set_qregci##mode (__o, \ - (signedtype) __temp.val[0], 0); \ - __o = __builtin_aarch64_set_qregci##mode (__o, \ - (signedtype) __temp.val[1], 1); \ - __o = __builtin_aarch64_set_qregci##mode (__o, \ - (signedtype) __temp.val[2], 2); \ + __o = __builtin_aarch64_set_qregci##qmode (__o, \ + (signedtype) __temp.val[0], 0); \ + __o = __builtin_aarch64_set_qregci##qmode (__o, \ + (signedtype) __temp.val[1], 1); \ + __o = __builtin_aarch64_set_qregci##qmode (__o, \ + (signedtype) __temp.val[2], 2); \ __builtin_aarch64_st3_lane##mode ((__builtin_aarch64_simd_ ## ptr_mode *) \ __ptr, __o, __c); \ } -__ST3_LANE_FUNC (float32x2x3_t, float32x4x3_t, float32_t, v4sf, sf, f32, +__ST3_LANE_FUNC (float32x2x3_t, float32x4x3_t, float32_t, v2sf, v4sf, sf, f32, float32x4_t) -__ST3_LANE_FUNC (float64x1x3_t, float64x2x3_t, float64_t, v2df, df, f64, +__ST3_LANE_FUNC (float64x1x3_t, float64x2x3_t, float64_t, df, v2df, df, f64, float64x2_t) -__ST3_LANE_FUNC (poly8x8x3_t, poly8x16x3_t, poly8_t, v16qi, qi, p8, int8x16_t) -__ST3_LANE_FUNC (poly16x4x3_t, poly16x8x3_t, poly16_t, v8hi, hi, p16, +__ST3_LANE_FUNC (poly8x8x3_t, poly8x16x3_t, poly8_t, v8qi, v16qi, qi, p8, + int8x16_t) +__ST3_LANE_FUNC (poly16x4x3_t, poly16x8x3_t, poly16_t, v4hi, v8hi, hi, p16, + int16x8_t) +__ST3_LANE_FUNC (int8x8x3_t, int8x16x3_t, int8_t, v8qi, v16qi, qi, s8, + int8x16_t) +__ST3_LANE_FUNC (int16x4x3_t, int16x8x3_t, int16_t, v4hi, v8hi, hi, s16, int16x8_t) -__ST3_LANE_FUNC (int8x8x3_t, int8x16x3_t, int8_t, v16qi, qi, s8, int8x16_t) -__ST3_LANE_FUNC (int16x4x3_t, int16x8x3_t, int16_t, v8hi, hi, s16, int16x8_t) -__ST3_LANE_FUNC (int32x2x3_t, int32x4x3_t, int32_t, v4si, si, s32, int32x4_t) -__ST3_LANE_FUNC (int64x1x3_t, int64x2x3_t, int64_t, v2di, di, s64, int64x2_t) -__ST3_LANE_FUNC (uint8x8x3_t, uint8x16x3_t, uint8_t, v16qi, qi, u8, int8x16_t) -__ST3_LANE_FUNC (uint16x4x3_t, uint16x8x3_t, uint16_t, v8hi, hi, u16, +__ST3_LANE_FUNC (int32x2x3_t, int32x4x3_t, int32_t, v2si, v4si, si, s32, + int32x4_t) +__ST3_LANE_FUNC (int64x1x3_t, int64x2x3_t, int64_t, di, v2di, di, s64, + int64x2_t) +__ST3_LANE_FUNC (uint8x8x3_t, uint8x16x3_t, uint8_t, v8qi, v16qi, qi, u8, + int8x16_t) +__ST3_LANE_FUNC (uint16x4x3_t, uint16x8x3_t, uint16_t, v4hi, v8hi, hi, u16, int16x8_t) -__ST3_LANE_FUNC (uint32x2x3_t, uint32x4x3_t, uint32_t, v4si, si, u32, +__ST3_LANE_FUNC (uint32x2x3_t, uint32x4x3_t, uint32_t, v2si, v4si, si, u32, int32x4_t) -__ST3_LANE_FUNC (uint64x1x3_t, uint64x2x3_t, uint64_t, v2di, di, u64, +__ST3_LANE_FUNC (uint64x1x3_t, uint64x2x3_t, uint64_t, di, v2di, di, u64, int64x2_t) #undef __ST3_LANE_FUNC @@ -10091,8 +10103,8 @@ __ST3_LANE_FUNC (uint16x8x3_t, uint16_t, v8hi, hi, u16) __ST3_LANE_FUNC (uint32x4x3_t, uint32_t, v4si, si, u32) __ST3_LANE_FUNC (uint64x2x3_t, uint64_t, v2di, di, u64) -#define __ST4_LANE_FUNC(intype, largetype, ptrtype, \ - mode, ptr_mode, funcsuffix, signedtype) \ +#define __ST4_LANE_FUNC(intype, largetype, ptrtype, mode, \ + qmode, ptr_mode, funcsuffix, signedtype) \ __extension__ static __inline void \ __attribute__ ((__always_inline__)) \ vst4_lane_ ## funcsuffix (ptrtype *__ptr, \ @@ -10112,35 +10124,41 @@ vst4_lane_ ## funcsuffix (ptrtype *__ptr, \ __temp.val[3] \ = vcombine_##funcsuffix (__b.val[3], \ vcreate_##funcsuffix (__AARCH64_UINT64_C (0))); \ - __o = __builtin_aarch64_set_qregxi##mode (__o, \ - (signedtype) __temp.val[0], 0); \ - __o = __builtin_aarch64_set_qregxi##mode (__o, \ - (signedtype) __temp.val[1], 1); \ - __o = __builtin_aarch64_set_qregxi##mode (__o, \ - (signedtype) __temp.val[2], 2); \ - __o = __builtin_aarch64_set_qregxi##mode (__o, \ - (signedtype) __temp.val[3], 3); \ + __o = __builtin_aarch64_set_qregxi##qmode (__o, \ + (signedtype) __temp.val[0], 0); \ + __o = __builtin_aarch64_set_qregxi##qmode (__o, \ + (signedtype) __temp.val[1], 1); \ + __o = __builtin_aarch64_set_qregxi##qmode (__o, \ + (signedtype) __temp.val[2], 2); \ + __o = __builtin_aarch64_set_qregxi##qmode (__o, \ + (signedtype) __temp.val[3], 3); \ __builtin_aarch64_st4_lane##mode ((__builtin_aarch64_simd_ ## ptr_mode *) \ __ptr, __o, __c); \ } -__ST4_LANE_FUNC (float32x2x4_t, float32x4x4_t, float32_t, v4sf, sf, f32, +__ST4_LANE_FUNC (float32x2x4_t, float32x4x4_t, float32_t, v2sf, v4sf, sf, f32, float32x4_t) -__ST4_LANE_FUNC (float64x1x4_t, float64x2x4_t, float64_t, v2df, df, f64, +__ST4_LANE_FUNC (float64x1x4_t, float64x2x4_t, float64_t, df, v2df, df, f64, float64x2_t) -__ST4_LANE_FUNC (poly8x8x4_t, poly8x16x4_t, poly8_t, v16qi, qi, p8, int8x16_t) -__ST4_LANE_FUNC (poly16x4x4_t, poly16x8x4_t, poly16_t, v8hi, hi, p16, +__ST4_LANE_FUNC (poly8x8x4_t, poly8x16x4_t, poly8_t, v8qi, v16qi, qi, p8, + int8x16_t) +__ST4_LANE_FUNC (poly16x4x4_t, poly16x8x4_t, poly16_t, v4hi, v8hi, hi, p16, int16x8_t) -__ST4_LANE_FUNC (int8x8x4_t, int8x16x4_t, int8_t, v16qi, qi, s8, int8x16_t) -__ST4_LANE_FUNC (int16x4x4_t, int16x8x4_t, int16_t, v8hi, hi, s16, int16x8_t) -__ST4_LANE_FUNC (int32x2x4_t, int32x4x4_t, int32_t, v4si, si, s32, int32x4_t) -__ST4_LANE_FUNC (int64x1x4_t, int64x2x4_t, int64_t, v2di, di, s64, int64x2_t) -__ST4_LANE_FUNC (uint8x8x4_t, uint8x16x4_t, uint8_t, v16qi, qi, u8, int8x16_t) -__ST4_LANE_FUNC (uint16x4x4_t, uint16x8x4_t, uint16_t, v8hi, hi, u16, +__ST4_LANE_FUNC (int8x8x4_t, int8x16x4_t, int8_t, v8qi, v16qi, qi, s8, + int8x16_t) +__ST4_LANE_FUNC (int16x4x4_t, int16x8x4_t, int16_t, v4hi, v8hi, hi, s16, + int16x8_t) +__ST4_LANE_FUNC (int32x2x4_t, int32x4x4_t, int32_t, v2si, v4si, si, s32, + int32x4_t) +__ST4_LANE_FUNC (int64x1x4_t, int64x2x4_t, int64_t, di, v2di, di, s64, + int64x2_t) +__ST4_LANE_FUNC (uint8x8x4_t, uint8x16x4_t, uint8_t, v8qi, v16qi, qi, u8, + int8x16_t) +__ST4_LANE_FUNC (uint16x4x4_t, uint16x8x4_t, uint16_t, v4hi, v8hi, hi, u16, int16x8_t) -__ST4_LANE_FUNC (uint32x2x4_t, uint32x4x4_t, uint32_t, v4si, si, u32, +__ST4_LANE_FUNC (uint32x2x4_t, uint32x4x4_t, uint32_t, v2si, v4si, si, u32, int32x4_t) -__ST4_LANE_FUNC (uint64x1x4_t, uint64x2x4_t, uint64_t, v2di, di, u64, +__ST4_LANE_FUNC (uint64x1x4_t, uint64x2x4_t, uint64_t, di, v2di, di, u64, int64x2_t) #undef __ST4_LANE_FUNC @@ -16799,8 +16817,8 @@ vld4q_dup_f64 (const float64_t * __a) /* vld2_lane */ -#define __LD2_LANE_FUNC(intype, vectype, largetype, ptrtype, \ - mode, ptrmode, funcsuffix, signedtype) \ +#define __LD2_LANE_FUNC(intype, vectype, largetype, ptrtype, mode, \ + qmode, ptrmode, funcsuffix, signedtype) \ __extension__ static __inline intype __attribute__ ((__always_inline__)) \ vld2_lane_##funcsuffix (const ptrtype * __ptr, intype __b, const int __c) \ { \ @@ -16810,12 +16828,12 @@ vld2_lane_##funcsuffix (const ptrtype * __ptr, intype __b, const int __c) \ vcombine_##funcsuffix (__b.val[0], vcreate_##funcsuffix (0)); \ __temp.val[1] = \ vcombine_##funcsuffix (__b.val[1], vcreate_##funcsuffix (0)); \ - __o = __builtin_aarch64_set_qregoi##mode (__o, \ - (signedtype) __temp.val[0], \ - 0); \ - __o = __builtin_aarch64_set_qregoi##mode (__o, \ - (signedtype) __temp.val[1], \ - 1); \ + __o = __builtin_aarch64_set_qregoi##qmode (__o, \ + (signedtype) __temp.val[0], \ + 0); \ + __o = __builtin_aarch64_set_qregoi##qmode (__o, \ + (signedtype) __temp.val[1], \ + 1); \ __o = __builtin_aarch64_ld2_lane##mode ( \ (__builtin_aarch64_simd_##ptrmode *) __ptr, __o, __c); \ __b.val[0] = (vectype) __builtin_aarch64_get_dregoidi (__o, 0); \ @@ -16823,29 +16841,29 @@ vld2_lane_##funcsuffix (const ptrtype * __ptr, intype __b, const int __c) \ return __b; \ } -__LD2_LANE_FUNC (float32x2x2_t, float32x2_t, float32x4x2_t, float32_t, v4sf, +__LD2_LANE_FUNC (float32x2x2_t, float32x2_t, float32x4x2_t, float32_t, v2sf, v4sf, sf, f32, float32x4_t) -__LD2_LANE_FUNC (float64x1x2_t, float64x1_t, float64x2x2_t, float64_t, v2df, +__LD2_LANE_FUNC (float64x1x2_t, float64x1_t, float64x2x2_t, float64_t, df, v2df, df, f64, float64x2_t) -__LD2_LANE_FUNC (poly8x8x2_t, poly8x8_t, poly8x16x2_t, poly8_t, v16qi, qi, p8, +__LD2_LANE_FUNC (poly8x8x2_t, poly8x8_t, poly8x16x2_t, poly8_t, v8qi, v16qi, qi, p8, int8x16_t) -__LD2_LANE_FUNC (poly16x4x2_t, poly16x4_t, poly16x8x2_t, poly16_t, v8hi, hi, +__LD2_LANE_FUNC (poly16x4x2_t, poly16x4_t, poly16x8x2_t, poly16_t, v4hi, v8hi, hi, p16, int16x8_t) -__LD2_LANE_FUNC (int8x8x2_t, int8x8_t, int8x16x2_t, int8_t, v16qi, qi, s8, +__LD2_LANE_FUNC (int8x8x2_t, int8x8_t, int8x16x2_t, int8_t, v8qi, v16qi, qi, s8, int8x16_t) -__LD2_LANE_FUNC (int16x4x2_t, int16x4_t, int16x8x2_t, int16_t, v8hi, hi, s16, +__LD2_LANE_FUNC (int16x4x2_t, int16x4_t, int16x8x2_t, int16_t, v4hi, v8hi, hi, s16, int16x8_t) -__LD2_LANE_FUNC (int32x2x2_t, int32x2_t, int32x4x2_t, int32_t, v4si, si, s32, +__LD2_LANE_FUNC (int32x2x2_t, int32x2_t, int32x4x2_t, int32_t, v2si, v4si, si, s32, int32x4_t) -__LD2_LANE_FUNC (int64x1x2_t, int64x1_t, int64x2x2_t, int64_t, v2di, di, s64, +__LD2_LANE_FUNC (int64x1x2_t, int64x1_t, int64x2x2_t, int64_t, di, v2di, di, s64, int64x2_t) -__LD2_LANE_FUNC (uint8x8x2_t, uint8x8_t, uint8x16x2_t, uint8_t, v16qi, qi, u8, +__LD2_LANE_FUNC (uint8x8x2_t, uint8x8_t, uint8x16x2_t, uint8_t, v8qi, v16qi, qi, u8, int8x16_t) -__LD2_LANE_FUNC (uint16x4x2_t, uint16x4_t, uint16x8x2_t, uint16_t, v8hi, hi, +__LD2_LANE_FUNC (uint16x4x2_t, uint16x4_t, uint16x8x2_t, uint16_t, v4hi, v8hi, hi, u16, int16x8_t) -__LD2_LANE_FUNC (uint32x2x2_t, uint32x2_t, uint32x4x2_t, uint32_t, v4si, si, +__LD2_LANE_FUNC (uint32x2x2_t, uint32x2_t, uint32x4x2_t, uint32_t, v2si, v4si, si, u32, int32x4_t) -__LD2_LANE_FUNC (uint64x1x2_t, uint64x1_t, uint64x2x2_t, uint64_t, v2di, di, +__LD2_LANE_FUNC (uint64x1x2_t, uint64x1_t, uint64x2x2_t, uint64_t, di, v2di, di, u64, int64x2_t) #undef __LD2_LANE_FUNC @@ -16884,8 +16902,8 @@ __LD2_LANE_FUNC (uint64x2x2_t, uint64x2_t, uint64_t, v2di, di, u64) /* vld3_lane */ -#define __LD3_LANE_FUNC(intype, vectype, largetype, ptrtype, \ - mode, ptrmode, funcsuffix, signedtype) \ +#define __LD3_LANE_FUNC(intype, vectype, largetype, ptrtype, mode, \ + qmode, ptrmode, funcsuffix, signedtype) \ __extension__ static __inline intype __attribute__ ((__always_inline__)) \ vld3_lane_##funcsuffix (const ptrtype * __ptr, intype __b, const int __c) \ { \ @@ -16897,15 +16915,15 @@ vld3_lane_##funcsuffix (const ptrtype * __ptr, intype __b, const int __c) \ vcombine_##funcsuffix (__b.val[1], vcreate_##funcsuffix (0)); \ __temp.val[2] = \ vcombine_##funcsuffix (__b.val[2], vcreate_##funcsuffix (0)); \ - __o = __builtin_aarch64_set_qregci##mode (__o, \ - (signedtype) __temp.val[0], \ - 0); \ - __o = __builtin_aarch64_set_qregci##mode (__o, \ - (signedtype) __temp.val[1], \ - 1); \ - __o = __builtin_aarch64_set_qregci##mode (__o, \ - (signedtype) __temp.val[2], \ - 2); \ + __o = __builtin_aarch64_set_qregci##qmode (__o, \ + (signedtype) __temp.val[0], \ + 0); \ + __o = __builtin_aarch64_set_qregci##qmode (__o, \ + (signedtype) __temp.val[1], \ + 1); \ + __o = __builtin_aarch64_set_qregci##qmode (__o, \ + (signedtype) __temp.val[2], \ + 2); \ __o = __builtin_aarch64_ld3_lane##mode ( \ (__builtin_aarch64_simd_##ptrmode *) __ptr, __o, __c); \ __b.val[0] = (vectype) __builtin_aarch64_get_dregcidi (__o, 0); \ @@ -16914,29 +16932,29 @@ vld3_lane_##funcsuffix (const ptrtype * __ptr, intype __b, const int __c) \ return __b; \ } -__LD3_LANE_FUNC (float32x2x3_t, float32x2_t, float32x4x3_t, float32_t, v4sf, +__LD3_LANE_FUNC (float32x2x3_t, float32x2_t, float32x4x3_t, float32_t, v2sf, v4sf, sf, f32, float32x4_t) -__LD3_LANE_FUNC (float64x1x3_t, float64x1_t, float64x2x3_t, float64_t, v2df, +__LD3_LANE_FUNC (float64x1x3_t, float64x1_t, float64x2x3_t, float64_t, df, v2df, df, f64, float64x2_t) -__LD3_LANE_FUNC (poly8x8x3_t, poly8x8_t, poly8x16x3_t, poly8_t, v16qi, qi, p8, +__LD3_LANE_FUNC (poly8x8x3_t, poly8x8_t, poly8x16x3_t, poly8_t, v8qi, v16qi, qi, p8, int8x16_t) -__LD3_LANE_FUNC (poly16x4x3_t, poly16x4_t, poly16x8x3_t, poly16_t, v8hi, hi, +__LD3_LANE_FUNC (poly16x4x3_t, poly16x4_t, poly16x8x3_t, poly16_t, v4hi, v8hi, hi, p16, int16x8_t) -__LD3_LANE_FUNC (int8x8x3_t, int8x8_t, int8x16x3_t, int8_t, v16qi, qi, s8, +__LD3_LANE_FUNC (int8x8x3_t, int8x8_t, int8x16x3_t, int8_t, v8qi, v16qi, qi, s8, int8x16_t) -__LD3_LANE_FUNC (int16x4x3_t, int16x4_t, int16x8x3_t, int16_t, v8hi, hi, s16, +__LD3_LANE_FUNC (int16x4x3_t, int16x4_t, int16x8x3_t, int16_t, v4hi, v8hi, hi, s16, int16x8_t) -__LD3_LANE_FUNC (int32x2x3_t, int32x2_t, int32x4x3_t, int32_t, v4si, si, s32, +__LD3_LANE_FUNC (int32x2x3_t, int32x2_t, int32x4x3_t, int32_t, v2si, v4si, si, s32, int32x4_t) -__LD3_LANE_FUNC (int64x1x3_t, int64x1_t, int64x2x3_t, int64_t, v2di, di, s64, +__LD3_LANE_FUNC (int64x1x3_t, int64x1_t, int64x2x3_t, int64_t, di, v2di, di, s64, int64x2_t) -__LD3_LANE_FUNC (uint8x8x3_t, uint8x8_t, uint8x16x3_t, uint8_t, v16qi, qi, u8, +__LD3_LANE_FUNC (uint8x8x3_t, uint8x8_t, uint8x16x3_t, uint8_t, v8qi, v16qi, qi, u8, int8x16_t) -__LD3_LANE_FUNC (uint16x4x3_t, uint16x4_t, uint16x8x3_t, uint16_t, v8hi, hi, +__LD3_LANE_FUNC (uint16x4x3_t, uint16x4_t, uint16x8x3_t, uint16_t, v4hi, v8hi, hi, u16, int16x8_t) -__LD3_LANE_FUNC (uint32x2x3_t, uint32x2_t, uint32x4x3_t, uint32_t, v4si, si, +__LD3_LANE_FUNC (uint32x2x3_t, uint32x2_t, uint32x4x3_t, uint32_t, v2si, v4si, si, u32, int32x4_t) -__LD3_LANE_FUNC (uint64x1x3_t, uint64x1_t, uint64x2x3_t, uint64_t, v2di, di, +__LD3_LANE_FUNC (uint64x1x3_t, uint64x1_t, uint64x2x3_t, uint64_t, di, v2di, di, u64, int64x2_t) #undef __LD3_LANE_FUNC @@ -16977,8 +16995,8 @@ __LD3_LANE_FUNC (uint64x2x3_t, uint64x2_t, uint64_t, v2di, di, u64) /* vld4_lane */ -#define __LD4_LANE_FUNC(intype, vectype, largetype, ptrtype, \ - mode, ptrmode, funcsuffix, signedtype) \ +#define __LD4_LANE_FUNC(intype, vectype, largetype, ptrtype, mode, \ + qmode, ptrmode, funcsuffix, signedtype) \ __extension__ static __inline intype __attribute__ ((__always_inline__)) \ vld4_lane_##funcsuffix (const ptrtype * __ptr, intype __b, const int __c) \ { \ @@ -16992,18 +17010,18 @@ vld4_lane_##funcsuffix (const ptrtype * __ptr, intype __b, const int __c) \ vcombine_##funcsuffix (__b.val[2], vcreate_##funcsuffix (0)); \ __temp.val[3] = \ vcombine_##funcsuffix (__b.val[3], vcreate_##funcsuffix (0)); \ - __o = __builtin_aarch64_set_qregxi##mode (__o, \ - (signedtype) __temp.val[0], \ - 0); \ - __o = __builtin_aarch64_set_qregxi##mode (__o, \ - (signedtype) __temp.val[1], \ - 1); \ - __o = __builtin_aarch64_set_qregxi##mode (__o, \ - (signedtype) __temp.val[2], \ - 2); \ - __o = __builtin_aarch64_set_qregxi##mode (__o, \ - (signedtype) __temp.val[3], \ - 3); \ + __o = __builtin_aarch64_set_qregxi##qmode (__o, \ + (signedtype) __temp.val[0], \ + 0); \ + __o = __builtin_aarch64_set_qregxi##qmode (__o, \ + (signedtype) __temp.val[1], \ + 1); \ + __o = __builtin_aarch64_set_qregxi##qmode (__o, \ + (signedtype) __temp.val[2], \ + 2); \ + __o = __builtin_aarch64_set_qregxi##qmode (__o, \ + (signedtype) __temp.val[3], \ + 3); \ __o = __builtin_aarch64_ld4_lane##mode ( \ (__builtin_aarch64_simd_##ptrmode *) __ptr, __o, __c); \ __b.val[0] = (vectype) __builtin_aarch64_get_dregxidi (__o, 0); \ @@ -17015,29 +17033,29 @@ vld4_lane_##funcsuffix (const ptrtype * __ptr, intype __b, const int __c) \ /* vld4q_lane */ -__LD4_LANE_FUNC (float32x2x4_t, float32x2_t, float32x4x4_t, float32_t, v4sf, +__LD4_LANE_FUNC (float32x2x4_t, float32x2_t, float32x4x4_t, float32_t, v2sf, v4sf, sf, f32, float32x4_t) -__LD4_LANE_FUNC (float64x1x4_t, float64x1_t, float64x2x4_t, float64_t, v2df, +__LD4_LANE_FUNC (float64x1x4_t, float64x1_t, float64x2x4_t, float64_t, df, v2df, df, f64, float64x2_t) -__LD4_LANE_FUNC (poly8x8x4_t, poly8x8_t, poly8x16x4_t, poly8_t, v16qi, qi, p8, +__LD4_LANE_FUNC (poly8x8x4_t, poly8x8_t, poly8x16x4_t, poly8_t, v8qi, v16qi, qi, p8, int8x16_t) -__LD4_LANE_FUNC (poly16x4x4_t, poly16x4_t, poly16x8x4_t, poly16_t, v8hi, hi, +__LD4_LANE_FUNC (poly16x4x4_t, poly16x4_t, poly16x8x4_t, poly16_t, v4hi, v8hi, hi, p16, int16x8_t) -__LD4_LANE_FUNC (int8x8x4_t, int8x8_t, int8x16x4_t, int8_t, v16qi, qi, s8, +__LD4_LANE_FUNC (int8x8x4_t, int8x8_t, int8x16x4_t, int8_t, v8qi, v16qi, qi, s8, int8x16_t) -__LD4_LANE_FUNC (int16x4x4_t, int16x4_t, int16x8x4_t, int16_t, v8hi, hi, s16, +__LD4_LANE_FUNC (int16x4x4_t, int16x4_t, int16x8x4_t, int16_t, v4hi, v8hi, hi, s16, int16x8_t) -__LD4_LANE_FUNC (int32x2x4_t, int32x2_t, int32x4x4_t, int32_t, v4si, si, s32, +__LD4_LANE_FUNC (int32x2x4_t, int32x2_t, int32x4x4_t, int32_t, v2si, v4si, si, s32, int32x4_t) -__LD4_LANE_FUNC (int64x1x4_t, int64x1_t, int64x2x4_t, int64_t, v2di, di, s64, +__LD4_LANE_FUNC (int64x1x4_t, int64x1_t, int64x2x4_t, int64_t, di, v2di, di, s64, int64x2_t) -__LD4_LANE_FUNC (uint8x8x4_t, uint8x8_t, uint8x16x4_t, uint8_t, v16qi, qi, u8, +__LD4_LANE_FUNC (uint8x8x4_t, uint8x8_t, uint8x16x4_t, uint8_t, v8qi, v16qi, qi, u8, int8x16_t) -__LD4_LANE_FUNC (uint16x4x4_t, uint16x4_t, uint16x8x4_t, uint16_t, v8hi, hi, +__LD4_LANE_FUNC (uint16x4x4_t, uint16x4_t, uint16x8x4_t, uint16_t, v4hi, v8hi, hi, u16, int16x8_t) -__LD4_LANE_FUNC (uint32x2x4_t, uint32x2_t, uint32x4x4_t, uint32_t, v4si, si, +__LD4_LANE_FUNC (uint32x2x4_t, uint32x2_t, uint32x4x4_t, uint32_t, v2si, v4si, si, u32, int32x4_t) -__LD4_LANE_FUNC (uint64x1x4_t, uint64x1_t, uint64x2x4_t, uint64_t, v2di, di, +__LD4_LANE_FUNC (uint64x1x4_t, uint64x1_t, uint64x2x4_t, uint64_t, di, v2di, di, u64, int64x2_t) #undef __LD4_LANE_FUNC diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 749b04fa3bd..80803088961 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,270 @@ +2015-07-22 Charles Baylis + + * gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f32_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f64_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vld2_lane_p8_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s16_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s32_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s64_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s8_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u16_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u32_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u64_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u8_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f32_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f64_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_p8_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s16_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s32_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s64_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s8_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u16_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u32_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u64_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u8_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f32_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f64_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vld3_lane_p8_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s16_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s32_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s64_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s8_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u16_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u32_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u64_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u8_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f32_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f64_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_p8_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s16_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s32_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s64_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s8_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u16_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u32_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u64_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u8_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f32_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f64_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vld4_lane_p8_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s16_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s32_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s64_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s8_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u16_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u32_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u64_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u8_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f32_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f64_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_p8_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s16_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s32_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s64_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s8_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u16_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u32_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u64_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u8_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f32_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f64_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vst2_lane_p8_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s16_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s32_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s64_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s8_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u16_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u32_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u64_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u8_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f32_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f64_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_p8_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s16_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s32_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s64_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s8_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u16_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u32_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u64_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u8_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f32_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f64_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vst3_lane_p8_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s16_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s32_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s64_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s8_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u16_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u32_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u64_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u8_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f32_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f64_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_p8_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s16_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s32_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s64_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s8_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u16_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u32_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u64_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u8_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f32_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f64_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vst4_lane_p8_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s16_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s32_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s64_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s8_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u16_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u32_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u64_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u8_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f32_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f64_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_p8_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s16_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s32_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s64_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s8_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u16_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u32_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u64_indices_1.c: New + test. + * gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u8_indices_1.c: New + test. + 2015-07-21 Paolo Carlini * g++.dg/template/crash81.C: Update. diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f32_indices_1.c new file mode 100644 index 00000000000..04be713d4bf --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f32_indices_1.c @@ -0,0 +1,16 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +float32x2x2_t +f_vld2_lane_f32 (float32_t * p, float32x2x2_t v) +{ + float32x2x2_t res; + /* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */ + res = vld2_lane_f32 (p, v, 2); + /* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */ + res = vld2_lane_f32 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f64_indices_1.c new file mode 100644 index 00000000000..a03d1653583 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f64_indices_1.c @@ -0,0 +1,17 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +float64x1x2_t +f_vld2_lane_f64 (float64_t * p, float64x1x2_t v) +{ + float64x1x2_t res; + /* { dg-error "lane 1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */ + res = vld2_lane_f64 (p, v, 1); + /* { dg-error "lane -1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */ + res = vld2_lane_f64 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_p8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_p8_indices_1.c new file mode 100644 index 00000000000..3a7aeb32a0e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_p8_indices_1.c @@ -0,0 +1,16 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +poly8x8x2_t +f_vld2_lane_p8 (poly8_t * p, poly8x8x2_t v) +{ + poly8x8x2_t res; + /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + res = vld2_lane_p8 (p, v, 8); + /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + res = vld2_lane_p8 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s16_indices_1.c new file mode 100644 index 00000000000..0b6314c8b66 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s16_indices_1.c @@ -0,0 +1,16 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +int16x4x2_t +f_vld2_lane_s16 (int16_t * p, int16x4x2_t v) +{ + int16x4x2_t res; + /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + res = vld2_lane_s16 (p, v, 4); + /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + res = vld2_lane_s16 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s32_indices_1.c new file mode 100644 index 00000000000..331478025b4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s32_indices_1.c @@ -0,0 +1,16 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +int32x2x2_t +f_vld2_lane_s32 (int32_t * p, int32x2x2_t v) +{ + int32x2x2_t res; + /* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */ + res = vld2_lane_s32 (p, v, 2); + /* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */ + res = vld2_lane_s32 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s64_indices_1.c new file mode 100644 index 00000000000..351ba40a69f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s64_indices_1.c @@ -0,0 +1,17 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +int64x1x2_t +f_vld2_lane_s64 (int64_t * p, int64x1x2_t v) +{ + int64x1x2_t res; + /* { dg-error "lane 1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */ + res = vld2_lane_s64 (p, v, 1); + /* { dg-error "lane -1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */ + res = vld2_lane_s64 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s8_indices_1.c new file mode 100644 index 00000000000..1db7462ba05 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s8_indices_1.c @@ -0,0 +1,16 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +int8x8x2_t +f_vld2_lane_s8 (int8_t * p, int8x8x2_t v) +{ + int8x8x2_t res; + /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + res = vld2_lane_s8 (p, v, 8); + /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + res = vld2_lane_s8 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u16_indices_1.c new file mode 100644 index 00000000000..b65ae561f9b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u16_indices_1.c @@ -0,0 +1,16 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +uint16x4x2_t +f_vld2_lane_u16 (uint16_t * p, uint16x4x2_t v) +{ + uint16x4x2_t res; + /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + res = vld2_lane_u16 (p, v, 4); + /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + res = vld2_lane_u16 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u32_indices_1.c new file mode 100644 index 00000000000..4990ed0ed02 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u32_indices_1.c @@ -0,0 +1,16 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +uint32x2x2_t +f_vld2_lane_u32 (uint32_t * p, uint32x2x2_t v) +{ + uint32x2x2_t res; + /* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */ + res = vld2_lane_u32 (p, v, 2); + /* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */ + res = vld2_lane_u32 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u64_indices_1.c new file mode 100644 index 00000000000..09ff01c54f2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u64_indices_1.c @@ -0,0 +1,17 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +uint64x1x2_t +f_vld2_lane_u64 (uint64_t * p, uint64x1x2_t v) +{ + uint64x1x2_t res; + /* { dg-error "lane 1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */ + res = vld2_lane_u64 (p, v, 1); + /* { dg-error "lane -1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */ + res = vld2_lane_u64 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u8_indices_1.c new file mode 100644 index 00000000000..d0c40a13ad1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u8_indices_1.c @@ -0,0 +1,16 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +uint8x8x2_t +f_vld2_lane_u8 (uint8_t * p, uint8x8x2_t v) +{ + uint8x8x2_t res; + /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + res = vld2_lane_u8 (p, v, 8); + /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + res = vld2_lane_u8 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f32_indices_1.c new file mode 100644 index 00000000000..84853f3522e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f32_indices_1.c @@ -0,0 +1,16 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +float32x4x2_t +f_vld2q_lane_f32 (float32_t * p, float32x4x2_t v) +{ + float32x4x2_t res; + /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + res = vld2q_lane_f32 (p, v, 4); + /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + res = vld2q_lane_f32 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f64_indices_1.c new file mode 100644 index 00000000000..4f106bc9b47 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f64_indices_1.c @@ -0,0 +1,17 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +float64x2x2_t +f_vld2q_lane_f64 (float64_t * p, float64x2x2_t v) +{ + float64x2x2_t res; + /* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */ + res = vld2q_lane_f64 (p, v, 2); + /* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */ + res = vld2q_lane_f64 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_p8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_p8_indices_1.c new file mode 100644 index 00000000000..04eab142715 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_p8_indices_1.c @@ -0,0 +1,17 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +poly8x16x2_t +f_vld2q_lane_p8 (poly8_t * p, poly8x16x2_t v) +{ + poly8x16x2_t res; + /* { dg-error "lane 16 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */ + res = vld2q_lane_p8 (p, v, 16); + /* { dg-error "lane -1 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */ + res = vld2q_lane_p8 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s16_indices_1.c new file mode 100644 index 00000000000..048517d5f08 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s16_indices_1.c @@ -0,0 +1,16 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +int16x8x2_t +f_vld2q_lane_s16 (int16_t * p, int16x8x2_t v) +{ + int16x8x2_t res; + /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + res = vld2q_lane_s16 (p, v, 8); + /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + res = vld2q_lane_s16 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s32_indices_1.c new file mode 100644 index 00000000000..620bafb53b3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s32_indices_1.c @@ -0,0 +1,16 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +int32x4x2_t +f_vld2q_lane_s32 (int32_t * p, int32x4x2_t v) +{ + int32x4x2_t res; + /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + res = vld2q_lane_s32 (p, v, 4); + /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + res = vld2q_lane_s32 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s64_indices_1.c new file mode 100644 index 00000000000..e182c6d5c1e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s64_indices_1.c @@ -0,0 +1,17 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +int64x2x2_t +f_vld2q_lane_s64 (int64_t * p, int64x2x2_t v) +{ + int64x2x2_t res; + /* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */ + res = vld2q_lane_s64 (p, v, 2); + /* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */ + res = vld2q_lane_s64 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s8_indices_1.c new file mode 100644 index 00000000000..a58538e02ad --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s8_indices_1.c @@ -0,0 +1,17 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +int8x16x2_t +f_vld2q_lane_s8 (int8_t * p, int8x16x2_t v) +{ + int8x16x2_t res; + /* { dg-error "lane 16 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */ + res = vld2q_lane_s8 (p, v, 16); + /* { dg-error "lane -1 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */ + res = vld2q_lane_s8 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u16_indices_1.c new file mode 100644 index 00000000000..cf6e9a12f99 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u16_indices_1.c @@ -0,0 +1,16 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +uint16x8x2_t +f_vld2q_lane_u16 (uint16_t * p, uint16x8x2_t v) +{ + uint16x8x2_t res; + /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + res = vld2q_lane_u16 (p, v, 8); + /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + res = vld2q_lane_u16 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u32_indices_1.c new file mode 100644 index 00000000000..6945cf0d912 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u32_indices_1.c @@ -0,0 +1,16 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +uint32x4x2_t +f_vld2q_lane_u32 (uint32_t * p, uint32x4x2_t v) +{ + uint32x4x2_t res; + /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + res = vld2q_lane_u32 (p, v, 4); + /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + res = vld2q_lane_u32 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u64_indices_1.c new file mode 100644 index 00000000000..84f09594922 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u64_indices_1.c @@ -0,0 +1,17 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +uint64x2x2_t +f_vld2q_lane_u64 (uint64_t * p, uint64x2x2_t v) +{ + uint64x2x2_t res; + /* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */ + res = vld2q_lane_u64 (p, v, 2); + /* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */ + res = vld2q_lane_u64 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u8_indices_1.c new file mode 100644 index 00000000000..82ecfe25484 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u8_indices_1.c @@ -0,0 +1,17 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +uint8x16x2_t +f_vld2q_lane_u8 (uint8_t * p, uint8x16x2_t v) +{ + uint8x16x2_t res; + /* { dg-error "lane 16 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */ + res = vld2q_lane_u8 (p, v, 16); + /* { dg-error "lane -1 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */ + res = vld2q_lane_u8 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f32_indices_1.c new file mode 100644 index 00000000000..4db8b7ca02b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f32_indices_1.c @@ -0,0 +1,16 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +float32x2x3_t +f_vld3_lane_f32 (float32_t * p, float32x2x3_t v) +{ + float32x2x3_t res; + /* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */ + res = vld3_lane_f32 (p, v, 2); + /* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */ + res = vld3_lane_f32 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f64_indices_1.c new file mode 100644 index 00000000000..74659768b92 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f64_indices_1.c @@ -0,0 +1,17 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +float64x1x3_t +f_vld3_lane_f64 (float64_t * p, float64x1x3_t v) +{ + float64x1x3_t res; + /* { dg-error "lane 1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */ + res = vld3_lane_f64 (p, v, 1); + /* { dg-error "lane -1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */ + res = vld3_lane_f64 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_p8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_p8_indices_1.c new file mode 100644 index 00000000000..712c67c72c7 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_p8_indices_1.c @@ -0,0 +1,16 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +poly8x8x3_t +f_vld3_lane_p8 (poly8_t * p, poly8x8x3_t v) +{ + poly8x8x3_t res; + /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + res = vld3_lane_p8 (p, v, 8); + /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + res = vld3_lane_p8 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s16_indices_1.c new file mode 100644 index 00000000000..22e11d39316 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s16_indices_1.c @@ -0,0 +1,16 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +int16x4x3_t +f_vld3_lane_s16 (int16_t * p, int16x4x3_t v) +{ + int16x4x3_t res; + /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + res = vld3_lane_s16 (p, v, 4); + /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + res = vld3_lane_s16 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s32_indices_1.c new file mode 100644 index 00000000000..ed4f50bea4c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s32_indices_1.c @@ -0,0 +1,16 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +int32x2x3_t +f_vld3_lane_s32 (int32_t * p, int32x2x3_t v) +{ + int32x2x3_t res; + /* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */ + res = vld3_lane_s32 (p, v, 2); + /* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */ + res = vld3_lane_s32 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s64_indices_1.c new file mode 100644 index 00000000000..ae7b35e4ccf --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s64_indices_1.c @@ -0,0 +1,17 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +int64x1x3_t +f_vld3_lane_s64 (int64_t * p, int64x1x3_t v) +{ + int64x1x3_t res; + /* { dg-error "lane 1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */ + res = vld3_lane_s64 (p, v, 1); + /* { dg-error "lane -1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */ + res = vld3_lane_s64 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s8_indices_1.c new file mode 100644 index 00000000000..320ef376af6 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s8_indices_1.c @@ -0,0 +1,16 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +int8x8x3_t +f_vld3_lane_s8 (int8_t * p, int8x8x3_t v) +{ + int8x8x3_t res; + /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + res = vld3_lane_s8 (p, v, 8); + /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + res = vld3_lane_s8 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u16_indices_1.c new file mode 100644 index 00000000000..a00253a345e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u16_indices_1.c @@ -0,0 +1,16 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +uint16x4x3_t +f_vld3_lane_u16 (uint16_t * p, uint16x4x3_t v) +{ + uint16x4x3_t res; + /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + res = vld3_lane_u16 (p, v, 4); + /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + res = vld3_lane_u16 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u32_indices_1.c new file mode 100644 index 00000000000..d53ead36796 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u32_indices_1.c @@ -0,0 +1,16 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +uint32x2x3_t +f_vld3_lane_u32 (uint32_t * p, uint32x2x3_t v) +{ + uint32x2x3_t res; + /* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */ + res = vld3_lane_u32 (p, v, 2); + /* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */ + res = vld3_lane_u32 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u64_indices_1.c new file mode 100644 index 00000000000..e9b44278d09 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u64_indices_1.c @@ -0,0 +1,17 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +uint64x1x3_t +f_vld3_lane_u64 (uint64_t * p, uint64x1x3_t v) +{ + uint64x1x3_t res; + /* { dg-error "lane 1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */ + res = vld3_lane_u64 (p, v, 1); + /* { dg-error "lane -1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */ + res = vld3_lane_u64 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u8_indices_1.c new file mode 100644 index 00000000000..3afff9f95d3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u8_indices_1.c @@ -0,0 +1,16 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +uint8x8x3_t +f_vld3_lane_u8 (uint8_t * p, uint8x8x3_t v) +{ + uint8x8x3_t res; + /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + res = vld3_lane_u8 (p, v, 8); + /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + res = vld3_lane_u8 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f32_indices_1.c new file mode 100644 index 00000000000..e38799cc540 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f32_indices_1.c @@ -0,0 +1,16 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +float32x4x3_t +f_vld3q_lane_f32 (float32_t * p, float32x4x3_t v) +{ + float32x4x3_t res; + /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + res = vld3q_lane_f32 (p, v, 4); + /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + res = vld3q_lane_f32 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f64_indices_1.c new file mode 100644 index 00000000000..c84c6c8e0da --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f64_indices_1.c @@ -0,0 +1,17 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +float64x2x3_t +f_vld3q_lane_f64 (float64_t * p, float64x2x3_t v) +{ + float64x2x3_t res; + /* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */ + res = vld3q_lane_f64 (p, v, 2); + /* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */ + res = vld3q_lane_f64 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_p8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_p8_indices_1.c new file mode 100644 index 00000000000..1dea0d4e895 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_p8_indices_1.c @@ -0,0 +1,17 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +poly8x16x3_t +f_vld3q_lane_p8 (poly8_t * p, poly8x16x3_t v) +{ + poly8x16x3_t res; + /* { dg-error "lane 16 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */ + res = vld3q_lane_p8 (p, v, 16); + /* { dg-error "lane -1 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */ + res = vld3q_lane_p8 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s16_indices_1.c new file mode 100644 index 00000000000..03f59f04926 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s16_indices_1.c @@ -0,0 +1,16 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +int16x8x3_t +f_vld3q_lane_s16 (int16_t * p, int16x8x3_t v) +{ + int16x8x3_t res; + /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + res = vld3q_lane_s16 (p, v, 8); + /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + res = vld3q_lane_s16 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s32_indices_1.c new file mode 100644 index 00000000000..57315ba9bca --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s32_indices_1.c @@ -0,0 +1,16 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +int32x4x3_t +f_vld3q_lane_s32 (int32_t * p, int32x4x3_t v) +{ + int32x4x3_t res; + /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + res = vld3q_lane_s32 (p, v, 4); + /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + res = vld3q_lane_s32 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s64_indices_1.c new file mode 100644 index 00000000000..fff4f80599d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s64_indices_1.c @@ -0,0 +1,17 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +int64x2x3_t +f_vld3q_lane_s64 (int64_t * p, int64x2x3_t v) +{ + int64x2x3_t res; + /* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */ + res = vld3q_lane_s64 (p, v, 2); + /* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */ + res = vld3q_lane_s64 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s8_indices_1.c new file mode 100644 index 00000000000..9c340e078ba --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s8_indices_1.c @@ -0,0 +1,17 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +int8x16x3_t +f_vld3q_lane_s8 (int8_t * p, int8x16x3_t v) +{ + int8x16x3_t res; + /* { dg-error "lane 16 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */ + res = vld3q_lane_s8 (p, v, 16); + /* { dg-error "lane -1 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */ + res = vld3q_lane_s8 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u16_indices_1.c new file mode 100644 index 00000000000..3dfaacbf970 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u16_indices_1.c @@ -0,0 +1,16 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +uint16x8x3_t +f_vld3q_lane_u16 (uint16_t * p, uint16x8x3_t v) +{ + uint16x8x3_t res; + /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + res = vld3q_lane_u16 (p, v, 8); + /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + res = vld3q_lane_u16 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u32_indices_1.c new file mode 100644 index 00000000000..9d4ed461a9d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u32_indices_1.c @@ -0,0 +1,16 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +uint32x4x3_t +f_vld3q_lane_u32 (uint32_t * p, uint32x4x3_t v) +{ + uint32x4x3_t res; + /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + res = vld3q_lane_u32 (p, v, 4); + /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + res = vld3q_lane_u32 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u64_indices_1.c new file mode 100644 index 00000000000..ca188a8748a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u64_indices_1.c @@ -0,0 +1,17 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +uint64x2x3_t +f_vld3q_lane_u64 (uint64_t * p, uint64x2x3_t v) +{ + uint64x2x3_t res; + /* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */ + res = vld3q_lane_u64 (p, v, 2); + /* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */ + res = vld3q_lane_u64 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u8_indices_1.c new file mode 100644 index 00000000000..5ca835ed2b1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u8_indices_1.c @@ -0,0 +1,17 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +uint8x16x3_t +f_vld3q_lane_u8 (uint8_t * p, uint8x16x3_t v) +{ + uint8x16x3_t res; + /* { dg-error "lane 16 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */ + res = vld3q_lane_u8 (p, v, 16); + /* { dg-error "lane -1 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */ + res = vld3q_lane_u8 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f32_indices_1.c new file mode 100644 index 00000000000..f956ee6b62d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f32_indices_1.c @@ -0,0 +1,16 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +float32x2x4_t +f_vld4_lane_f32 (float32_t * p, float32x2x4_t v) +{ + float32x2x4_t res; + /* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */ + res = vld4_lane_f32 (p, v, 2); + /* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */ + res = vld4_lane_f32 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f64_indices_1.c new file mode 100644 index 00000000000..52763b4903b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f64_indices_1.c @@ -0,0 +1,17 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +float64x1x4_t +f_vld4_lane_f64 (float64_t * p, float64x1x4_t v) +{ + float64x1x4_t res; + /* { dg-error "lane 1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */ + res = vld4_lane_f64 (p, v, 1); + /* { dg-error "lane -1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */ + res = vld4_lane_f64 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_p8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_p8_indices_1.c new file mode 100644 index 00000000000..8f9d3eeabdb --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_p8_indices_1.c @@ -0,0 +1,16 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +poly8x8x4_t +f_vld4_lane_p8 (poly8_t * p, poly8x8x4_t v) +{ + poly8x8x4_t res; + /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + res = vld4_lane_p8 (p, v, 8); + /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + res = vld4_lane_p8 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s16_indices_1.c new file mode 100644 index 00000000000..53f51a0f0b5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s16_indices_1.c @@ -0,0 +1,16 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +int16x4x4_t +f_vld4_lane_s16 (int16_t * p, int16x4x4_t v) +{ + int16x4x4_t res; + /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + res = vld4_lane_s16 (p, v, 4); + /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + res = vld4_lane_s16 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s32_indices_1.c new file mode 100644 index 00000000000..7b8396edab9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s32_indices_1.c @@ -0,0 +1,16 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +int32x2x4_t +f_vld4_lane_s32 (int32_t * p, int32x2x4_t v) +{ + int32x2x4_t res; + /* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */ + res = vld4_lane_s32 (p, v, 2); + /* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */ + res = vld4_lane_s32 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s64_indices_1.c new file mode 100644 index 00000000000..8cc138eadea --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s64_indices_1.c @@ -0,0 +1,17 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +int64x1x4_t +f_vld4_lane_s64 (int64_t * p, int64x1x4_t v) +{ + int64x1x4_t res; + /* { dg-error "lane 1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */ + res = vld4_lane_s64 (p, v, 1); + /* { dg-error "lane -1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */ + res = vld4_lane_s64 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s8_indices_1.c new file mode 100644 index 00000000000..1c3bcf375a7 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s8_indices_1.c @@ -0,0 +1,16 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +int8x8x4_t +f_vld4_lane_s8 (int8_t * p, int8x8x4_t v) +{ + int8x8x4_t res; + /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + res = vld4_lane_s8 (p, v, 8); + /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + res = vld4_lane_s8 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u16_indices_1.c new file mode 100644 index 00000000000..2ac73af886b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u16_indices_1.c @@ -0,0 +1,16 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +uint16x4x4_t +f_vld4_lane_u16 (uint16_t * p, uint16x4x4_t v) +{ + uint16x4x4_t res; + /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + res = vld4_lane_u16 (p, v, 4); + /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + res = vld4_lane_u16 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u32_indices_1.c new file mode 100644 index 00000000000..e37e03823c7 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u32_indices_1.c @@ -0,0 +1,16 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +uint32x2x4_t +f_vld4_lane_u32 (uint32_t * p, uint32x2x4_t v) +{ + uint32x2x4_t res; + /* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */ + res = vld4_lane_u32 (p, v, 2); + /* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */ + res = vld4_lane_u32 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u64_indices_1.c new file mode 100644 index 00000000000..96f0bb89645 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u64_indices_1.c @@ -0,0 +1,17 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +uint64x1x4_t +f_vld4_lane_u64 (uint64_t * p, uint64x1x4_t v) +{ + uint64x1x4_t res; + /* { dg-error "lane 1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */ + res = vld4_lane_u64 (p, v, 1); + /* { dg-error "lane -1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */ + res = vld4_lane_u64 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u8_indices_1.c new file mode 100644 index 00000000000..e8de33513ff --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u8_indices_1.c @@ -0,0 +1,16 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +uint8x8x4_t +f_vld4_lane_u8 (uint8_t * p, uint8x8x4_t v) +{ + uint8x8x4_t res; + /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + res = vld4_lane_u8 (p, v, 8); + /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + res = vld4_lane_u8 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f32_indices_1.c new file mode 100644 index 00000000000..93d57302778 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f32_indices_1.c @@ -0,0 +1,16 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +float32x4x4_t +f_vld4q_lane_f32 (float32_t * p, float32x4x4_t v) +{ + float32x4x4_t res; + /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + res = vld4q_lane_f32 (p, v, 4); + /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + res = vld4q_lane_f32 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f64_indices_1.c new file mode 100644 index 00000000000..062e0ebaf00 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f64_indices_1.c @@ -0,0 +1,17 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +float64x2x4_t +f_vld4q_lane_f64 (float64_t * p, float64x2x4_t v) +{ + float64x2x4_t res; + /* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */ + res = vld4q_lane_f64 (p, v, 2); + /* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */ + res = vld4q_lane_f64 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_p8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_p8_indices_1.c new file mode 100644 index 00000000000..32ae95b9804 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_p8_indices_1.c @@ -0,0 +1,17 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +poly8x16x4_t +f_vld4q_lane_p8 (poly8_t * p, poly8x16x4_t v) +{ + poly8x16x4_t res; + /* { dg-error "lane 16 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */ + res = vld4q_lane_p8 (p, v, 16); + /* { dg-error "lane -1 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */ + res = vld4q_lane_p8 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s16_indices_1.c new file mode 100644 index 00000000000..f4a7225f3a3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s16_indices_1.c @@ -0,0 +1,16 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +int16x8x4_t +f_vld4q_lane_s16 (int16_t * p, int16x8x4_t v) +{ + int16x8x4_t res; + /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + res = vld4q_lane_s16 (p, v, 8); + /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + res = vld4q_lane_s16 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s32_indices_1.c new file mode 100644 index 00000000000..45dd197fe7b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s32_indices_1.c @@ -0,0 +1,16 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +int32x4x4_t +f_vld4q_lane_s32 (int32_t * p, int32x4x4_t v) +{ + int32x4x4_t res; + /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + res = vld4q_lane_s32 (p, v, 4); + /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + res = vld4q_lane_s32 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s64_indices_1.c new file mode 100644 index 00000000000..5a01d051b75 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s64_indices_1.c @@ -0,0 +1,17 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +int64x2x4_t +f_vld4q_lane_s64 (int64_t * p, int64x2x4_t v) +{ + int64x2x4_t res; + /* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */ + res = vld4q_lane_s64 (p, v, 2); + /* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */ + res = vld4q_lane_s64 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s8_indices_1.c new file mode 100644 index 00000000000..db6691791f8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s8_indices_1.c @@ -0,0 +1,17 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +int8x16x4_t +f_vld4q_lane_s8 (int8_t * p, int8x16x4_t v) +{ + int8x16x4_t res; + /* { dg-error "lane 16 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */ + res = vld4q_lane_s8 (p, v, 16); + /* { dg-error "lane -1 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */ + res = vld4q_lane_s8 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u16_indices_1.c new file mode 100644 index 00000000000..5a27639477c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u16_indices_1.c @@ -0,0 +1,16 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +uint16x8x4_t +f_vld4q_lane_u16 (uint16_t * p, uint16x8x4_t v) +{ + uint16x8x4_t res; + /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + res = vld4q_lane_u16 (p, v, 8); + /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + res = vld4q_lane_u16 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u32_indices_1.c new file mode 100644 index 00000000000..5d8a57080fe --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u32_indices_1.c @@ -0,0 +1,16 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +uint32x4x4_t +f_vld4q_lane_u32 (uint32_t * p, uint32x4x4_t v) +{ + uint32x4x4_t res; + /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + res = vld4q_lane_u32 (p, v, 4); + /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + res = vld4q_lane_u32 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u64_indices_1.c new file mode 100644 index 00000000000..92b4c517db2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u64_indices_1.c @@ -0,0 +1,17 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +uint64x2x4_t +f_vld4q_lane_u64 (uint64_t * p, uint64x2x4_t v) +{ + uint64x2x4_t res; + /* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */ + res = vld4q_lane_u64 (p, v, 2); + /* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */ + res = vld4q_lane_u64 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u8_indices_1.c new file mode 100644 index 00000000000..293416da9a4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u8_indices_1.c @@ -0,0 +1,17 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +uint8x16x4_t +f_vld4q_lane_u8 (uint8_t * p, uint8x16x4_t v) +{ + uint8x16x4_t res; + /* { dg-error "lane 16 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */ + res = vld4q_lane_u8 (p, v, 16); + /* { dg-error "lane -1 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */ + res = vld4q_lane_u8 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f32_indices_1.c new file mode 100644 index 00000000000..1a39625a604 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f32_indices_1.c @@ -0,0 +1,15 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +void +f_vst2_lane_f32 (float32_t * p, float32x2x2_t v) +{ + /* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */ + vst2_lane_f32 (p, v, 2); + /* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */ + vst2_lane_f32 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f64_indices_1.c new file mode 100644 index 00000000000..367471517ce --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f64_indices_1.c @@ -0,0 +1,16 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +void +f_vst2_lane_f64 (float64_t * p, float64x1x2_t v) +{ + /* { dg-error "lane 1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */ + vst2_lane_f64 (p, v, 1); + /* { dg-error "lane -1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */ + vst2_lane_f64 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_p8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_p8_indices_1.c new file mode 100644 index 00000000000..770fe9da3f0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_p8_indices_1.c @@ -0,0 +1,15 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +void +f_vst2_lane_p8 (poly8_t * p, poly8x8x2_t v) +{ + /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + vst2_lane_p8 (p, v, 8); + /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + vst2_lane_p8 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s16_indices_1.c new file mode 100644 index 00000000000..ac89d03b415 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s16_indices_1.c @@ -0,0 +1,15 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +void +f_vst2_lane_s16 (int16_t * p, int16x4x2_t v) +{ + /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + vst2_lane_s16 (p, v, 4); + /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + vst2_lane_s16 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s32_indices_1.c new file mode 100644 index 00000000000..4bbceb65437 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s32_indices_1.c @@ -0,0 +1,15 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +void +f_vst2_lane_s32 (int32_t * p, int32x2x2_t v) +{ + /* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */ + vst2_lane_s32 (p, v, 2); + /* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */ + vst2_lane_s32 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s64_indices_1.c new file mode 100644 index 00000000000..da60b9bfef1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s64_indices_1.c @@ -0,0 +1,16 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +void +f_vst2_lane_s64 (int64_t * p, int64x1x2_t v) +{ + /* { dg-error "lane 1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */ + vst2_lane_s64 (p, v, 1); + /* { dg-error "lane -1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */ + vst2_lane_s64 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s8_indices_1.c new file mode 100644 index 00000000000..b5bf3d685a7 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s8_indices_1.c @@ -0,0 +1,15 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +void +f_vst2_lane_s8 (int8_t * p, int8x8x2_t v) +{ + /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + vst2_lane_s8 (p, v, 8); + /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + vst2_lane_s8 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u16_indices_1.c new file mode 100644 index 00000000000..bfdc5c0b15c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u16_indices_1.c @@ -0,0 +1,15 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +void +f_vst2_lane_u16 (uint16_t * p, uint16x4x2_t v) +{ + /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + vst2_lane_u16 (p, v, 4); + /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + vst2_lane_u16 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u32_indices_1.c new file mode 100644 index 00000000000..e32c6ff3d63 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u32_indices_1.c @@ -0,0 +1,15 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +void +f_vst2_lane_u32 (uint32_t * p, uint32x2x2_t v) +{ + /* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */ + vst2_lane_u32 (p, v, 2); + /* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */ + vst2_lane_u32 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u64_indices_1.c new file mode 100644 index 00000000000..03546bdd97f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u64_indices_1.c @@ -0,0 +1,16 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +void +f_vst2_lane_u64 (uint64_t * p, uint64x1x2_t v) +{ + /* { dg-error "lane 1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */ + vst2_lane_u64 (p, v, 1); + /* { dg-error "lane -1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */ + vst2_lane_u64 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u8_indices_1.c new file mode 100644 index 00000000000..74da14c0305 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u8_indices_1.c @@ -0,0 +1,15 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +void +f_vst2_lane_u8 (uint8_t * p, uint8x8x2_t v) +{ + /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + vst2_lane_u8 (p, v, 8); + /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + vst2_lane_u8 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f32_indices_1.c new file mode 100644 index 00000000000..246c60cef01 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f32_indices_1.c @@ -0,0 +1,15 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +void +f_vst2q_lane_f32 (float32_t * p, float32x4x2_t v) +{ + /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + vst2q_lane_f32 (p, v, 4); + /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + vst2q_lane_f32 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f64_indices_1.c new file mode 100644 index 00000000000..a1029217975 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f64_indices_1.c @@ -0,0 +1,16 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +void +f_vst2q_lane_f64 (float64_t * p, float64x2x2_t v) +{ + /* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */ + vst2q_lane_f64 (p, v, 2); + /* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */ + vst2q_lane_f64 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_p8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_p8_indices_1.c new file mode 100644 index 00000000000..8966b539b83 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_p8_indices_1.c @@ -0,0 +1,16 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +void +f_vst2q_lane_p8 (poly8_t * p, poly8x16x2_t v) +{ + /* { dg-error "lane 16 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */ + vst2q_lane_p8 (p, v, 16); + /* { dg-error "lane -1 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */ + vst2q_lane_p8 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s16_indices_1.c new file mode 100644 index 00000000000..19d22a1f2b1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s16_indices_1.c @@ -0,0 +1,15 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +void +f_vst2q_lane_s16 (int16_t * p, int16x8x2_t v) +{ + /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + vst2q_lane_s16 (p, v, 8); + /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + vst2q_lane_s16 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s32_indices_1.c new file mode 100644 index 00000000000..bbb772c0ccf --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s32_indices_1.c @@ -0,0 +1,15 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +void +f_vst2q_lane_s32 (int32_t * p, int32x4x2_t v) +{ + /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + vst2q_lane_s32 (p, v, 4); + /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + vst2q_lane_s32 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s64_indices_1.c new file mode 100644 index 00000000000..6efc6813395 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s64_indices_1.c @@ -0,0 +1,16 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +void +f_vst2q_lane_s64 (int64_t * p, int64x2x2_t v) +{ + /* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */ + vst2q_lane_s64 (p, v, 2); + /* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */ + vst2q_lane_s64 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s8_indices_1.c new file mode 100644 index 00000000000..7c0eb499985 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s8_indices_1.c @@ -0,0 +1,16 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +void +f_vst2q_lane_s8 (int8_t * p, int8x16x2_t v) +{ + /* { dg-error "lane 16 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */ + vst2q_lane_s8 (p, v, 16); + /* { dg-error "lane -1 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */ + vst2q_lane_s8 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u16_indices_1.c new file mode 100644 index 00000000000..b079a34f75a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u16_indices_1.c @@ -0,0 +1,15 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +void +f_vst2q_lane_u16 (uint16_t * p, uint16x8x2_t v) +{ + /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + vst2q_lane_u16 (p, v, 8); + /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + vst2q_lane_u16 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u32_indices_1.c new file mode 100644 index 00000000000..b919e2b81fc --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u32_indices_1.c @@ -0,0 +1,15 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +void +f_vst2q_lane_u32 (uint32_t * p, uint32x4x2_t v) +{ + /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + vst2q_lane_u32 (p, v, 4); + /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + vst2q_lane_u32 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u64_indices_1.c new file mode 100644 index 00000000000..7d31d65ee90 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u64_indices_1.c @@ -0,0 +1,16 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +void +f_vst2q_lane_u64 (uint64_t * p, uint64x2x2_t v) +{ + /* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */ + vst2q_lane_u64 (p, v, 2); + /* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */ + vst2q_lane_u64 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u8_indices_1.c new file mode 100644 index 00000000000..9c35ce97570 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u8_indices_1.c @@ -0,0 +1,16 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +void +f_vst2q_lane_u8 (uint8_t * p, uint8x16x2_t v) +{ + /* { dg-error "lane 16 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */ + vst2q_lane_u8 (p, v, 16); + /* { dg-error "lane -1 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */ + vst2q_lane_u8 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f32_indices_1.c new file mode 100644 index 00000000000..1d7a57ef4c5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f32_indices_1.c @@ -0,0 +1,15 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +void +f_vst3_lane_f32 (float32_t * p, float32x2x3_t v) +{ + /* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */ + vst3_lane_f32 (p, v, 2); + /* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */ + vst3_lane_f32 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f64_indices_1.c new file mode 100644 index 00000000000..5e9b9ea91de --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f64_indices_1.c @@ -0,0 +1,16 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +void +f_vst3_lane_f64 (float64_t * p, float64x1x3_t v) +{ + /* { dg-error "lane 1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */ + vst3_lane_f64 (p, v, 1); + /* { dg-error "lane -1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */ + vst3_lane_f64 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_p8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_p8_indices_1.c new file mode 100644 index 00000000000..7599a19571c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_p8_indices_1.c @@ -0,0 +1,15 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +void +f_vst3_lane_p8 (poly8_t * p, poly8x8x3_t v) +{ + /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + vst3_lane_p8 (p, v, 8); + /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + vst3_lane_p8 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s16_indices_1.c new file mode 100644 index 00000000000..f8b856de6a8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s16_indices_1.c @@ -0,0 +1,15 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +void +f_vst3_lane_s16 (int16_t * p, int16x4x3_t v) +{ + /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + vst3_lane_s16 (p, v, 4); + /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + vst3_lane_s16 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s32_indices_1.c new file mode 100644 index 00000000000..7fbf2e896c7 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s32_indices_1.c @@ -0,0 +1,15 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +void +f_vst3_lane_s32 (int32_t * p, int32x2x3_t v) +{ + /* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */ + vst3_lane_s32 (p, v, 2); + /* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */ + vst3_lane_s32 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s64_indices_1.c new file mode 100644 index 00000000000..801dcc048cd --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s64_indices_1.c @@ -0,0 +1,16 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +void +f_vst3_lane_s64 (int64_t * p, int64x1x3_t v) +{ + /* { dg-error "lane 1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */ + vst3_lane_s64 (p, v, 1); + /* { dg-error "lane -1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */ + vst3_lane_s64 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s8_indices_1.c new file mode 100644 index 00000000000..1623326ceab --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s8_indices_1.c @@ -0,0 +1,15 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +void +f_vst3_lane_s8 (int8_t * p, int8x8x3_t v) +{ + /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + vst3_lane_s8 (p, v, 8); + /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + vst3_lane_s8 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u16_indices_1.c new file mode 100644 index 00000000000..7304da6504f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u16_indices_1.c @@ -0,0 +1,15 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +void +f_vst3_lane_u16 (uint16_t * p, uint16x4x3_t v) +{ + /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + vst3_lane_u16 (p, v, 4); + /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + vst3_lane_u16 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u32_indices_1.c new file mode 100644 index 00000000000..4c1c4b78846 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u32_indices_1.c @@ -0,0 +1,15 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +void +f_vst3_lane_u32 (uint32_t * p, uint32x2x3_t v) +{ + /* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */ + vst3_lane_u32 (p, v, 2); + /* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */ + vst3_lane_u32 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u64_indices_1.c new file mode 100644 index 00000000000..adc8fb2a15f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u64_indices_1.c @@ -0,0 +1,16 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +void +f_vst3_lane_u64 (uint64_t * p, uint64x1x3_t v) +{ + /* { dg-error "lane 1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */ + vst3_lane_u64 (p, v, 1); + /* { dg-error "lane -1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */ + vst3_lane_u64 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u8_indices_1.c new file mode 100644 index 00000000000..8a55b5539c0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u8_indices_1.c @@ -0,0 +1,15 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +void +f_vst3_lane_u8 (uint8_t * p, uint8x8x3_t v) +{ + /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + vst3_lane_u8 (p, v, 8); + /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + vst3_lane_u8 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f32_indices_1.c new file mode 100644 index 00000000000..8a081fef39b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f32_indices_1.c @@ -0,0 +1,15 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +void +f_vst3q_lane_f32 (float32_t * p, float32x4x3_t v) +{ + /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + vst3q_lane_f32 (p, v, 4); + /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + vst3q_lane_f32 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f64_indices_1.c new file mode 100644 index 00000000000..2d867f2dc11 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f64_indices_1.c @@ -0,0 +1,16 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +void +f_vst3q_lane_f64 (float64_t * p, float64x2x3_t v) +{ + /* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */ + vst3q_lane_f64 (p, v, 2); + /* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */ + vst3q_lane_f64 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_p8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_p8_indices_1.c new file mode 100644 index 00000000000..295f6b6fcb2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_p8_indices_1.c @@ -0,0 +1,16 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +void +f_vst3q_lane_p8 (poly8_t * p, poly8x16x3_t v) +{ + /* { dg-error "lane 16 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */ + vst3q_lane_p8 (p, v, 16); + /* { dg-error "lane -1 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */ + vst3q_lane_p8 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s16_indices_1.c new file mode 100644 index 00000000000..160c90c3996 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s16_indices_1.c @@ -0,0 +1,15 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +void +f_vst3q_lane_s16 (int16_t * p, int16x8x3_t v) +{ + /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + vst3q_lane_s16 (p, v, 8); + /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + vst3q_lane_s16 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s32_indices_1.c new file mode 100644 index 00000000000..0324f3ce11c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s32_indices_1.c @@ -0,0 +1,15 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +void +f_vst3q_lane_s32 (int32_t * p, int32x4x3_t v) +{ + /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + vst3q_lane_s32 (p, v, 4); + /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + vst3q_lane_s32 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s64_indices_1.c new file mode 100644 index 00000000000..b56512610e0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s64_indices_1.c @@ -0,0 +1,16 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +void +f_vst3q_lane_s64 (int64_t * p, int64x2x3_t v) +{ + /* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */ + vst3q_lane_s64 (p, v, 2); + /* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */ + vst3q_lane_s64 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s8_indices_1.c new file mode 100644 index 00000000000..5e35bb9959b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s8_indices_1.c @@ -0,0 +1,16 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +void +f_vst3q_lane_s8 (int8_t * p, int8x16x3_t v) +{ + /* { dg-error "lane 16 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */ + vst3q_lane_s8 (p, v, 16); + /* { dg-error "lane -1 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */ + vst3q_lane_s8 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u16_indices_1.c new file mode 100644 index 00000000000..9eaae3b66a4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u16_indices_1.c @@ -0,0 +1,15 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +void +f_vst3q_lane_u16 (uint16_t * p, uint16x8x3_t v) +{ + /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + vst3q_lane_u16 (p, v, 8); + /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + vst3q_lane_u16 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u32_indices_1.c new file mode 100644 index 00000000000..62339fcdb14 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u32_indices_1.c @@ -0,0 +1,15 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +void +f_vst3q_lane_u32 (uint32_t * p, uint32x4x3_t v) +{ + /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + vst3q_lane_u32 (p, v, 4); + /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + vst3q_lane_u32 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u64_indices_1.c new file mode 100644 index 00000000000..39044cc226d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u64_indices_1.c @@ -0,0 +1,16 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +void +f_vst3q_lane_u64 (uint64_t * p, uint64x2x3_t v) +{ + /* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */ + vst3q_lane_u64 (p, v, 2); + /* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */ + vst3q_lane_u64 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u8_indices_1.c new file mode 100644 index 00000000000..bf48dbb3d59 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u8_indices_1.c @@ -0,0 +1,16 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +void +f_vst3q_lane_u8 (uint8_t * p, uint8x16x3_t v) +{ + /* { dg-error "lane 16 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */ + vst3q_lane_u8 (p, v, 16); + /* { dg-error "lane -1 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */ + vst3q_lane_u8 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f32_indices_1.c new file mode 100644 index 00000000000..7f045120ef0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f32_indices_1.c @@ -0,0 +1,15 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +void +f_vst4_lane_f32 (float32_t * p, float32x2x4_t v) +{ + /* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */ + vst4_lane_f32 (p, v, 2); + /* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */ + vst4_lane_f32 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f64_indices_1.c new file mode 100644 index 00000000000..ddee219d376 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f64_indices_1.c @@ -0,0 +1,16 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +void +f_vst4_lane_f64 (float64_t * p, float64x1x4_t v) +{ + /* { dg-error "lane 1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */ + vst4_lane_f64 (p, v, 1); + /* { dg-error "lane -1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */ + vst4_lane_f64 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_p8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_p8_indices_1.c new file mode 100644 index 00000000000..14491acbff1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_p8_indices_1.c @@ -0,0 +1,15 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +void +f_vst4_lane_p8 (poly8_t * p, poly8x8x4_t v) +{ + /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + vst4_lane_p8 (p, v, 8); + /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + vst4_lane_p8 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s16_indices_1.c new file mode 100644 index 00000000000..8434a9b30ef --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s16_indices_1.c @@ -0,0 +1,15 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +void +f_vst4_lane_s16 (int16_t * p, int16x4x4_t v) +{ + /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + vst4_lane_s16 (p, v, 4); + /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + vst4_lane_s16 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s32_indices_1.c new file mode 100644 index 00000000000..53a4a46ae56 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s32_indices_1.c @@ -0,0 +1,15 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +void +f_vst4_lane_s32 (int32_t * p, int32x2x4_t v) +{ + /* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */ + vst4_lane_s32 (p, v, 2); + /* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */ + vst4_lane_s32 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s64_indices_1.c new file mode 100644 index 00000000000..051c8eb9fc2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s64_indices_1.c @@ -0,0 +1,16 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +void +f_vst4_lane_s64 (int64_t * p, int64x1x4_t v) +{ + /* { dg-error "lane 1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */ + vst4_lane_s64 (p, v, 1); + /* { dg-error "lane -1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */ + vst4_lane_s64 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s8_indices_1.c new file mode 100644 index 00000000000..33967ac515a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s8_indices_1.c @@ -0,0 +1,15 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +void +f_vst4_lane_s8 (int8_t * p, int8x8x4_t v) +{ + /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + vst4_lane_s8 (p, v, 8); + /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + vst4_lane_s8 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u16_indices_1.c new file mode 100644 index 00000000000..8e358dd7d6b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u16_indices_1.c @@ -0,0 +1,15 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +void +f_vst4_lane_u16 (uint16_t * p, uint16x4x4_t v) +{ + /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + vst4_lane_u16 (p, v, 4); + /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + vst4_lane_u16 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u32_indices_1.c new file mode 100644 index 00000000000..4f7899f04a2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u32_indices_1.c @@ -0,0 +1,15 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +void +f_vst4_lane_u32 (uint32_t * p, uint32x2x4_t v) +{ + /* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */ + vst4_lane_u32 (p, v, 2); + /* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */ + vst4_lane_u32 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u64_indices_1.c new file mode 100644 index 00000000000..9fb06d18097 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u64_indices_1.c @@ -0,0 +1,16 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +void +f_vst4_lane_u64 (uint64_t * p, uint64x1x4_t v) +{ + /* { dg-error "lane 1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */ + vst4_lane_u64 (p, v, 1); + /* { dg-error "lane -1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */ + vst4_lane_u64 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u8_indices_1.c new file mode 100644 index 00000000000..3a183224bc9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u8_indices_1.c @@ -0,0 +1,15 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +void +f_vst4_lane_u8 (uint8_t * p, uint8x8x4_t v) +{ + /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + vst4_lane_u8 (p, v, 8); + /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + vst4_lane_u8 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f32_indices_1.c new file mode 100644 index 00000000000..72f7d0287d8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f32_indices_1.c @@ -0,0 +1,15 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +void +f_vst4q_lane_f32 (float32_t * p, float32x4x4_t v) +{ + /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + vst4q_lane_f32 (p, v, 4); + /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + vst4q_lane_f32 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f64_indices_1.c new file mode 100644 index 00000000000..c5f721fbed2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f64_indices_1.c @@ -0,0 +1,16 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +void +f_vst4q_lane_f64 (float64_t * p, float64x2x4_t v) +{ + /* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */ + vst4q_lane_f64 (p, v, 2); + /* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */ + vst4q_lane_f64 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_p8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_p8_indices_1.c new file mode 100644 index 00000000000..3e57c954de6 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_p8_indices_1.c @@ -0,0 +1,16 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +void +f_vst4q_lane_p8 (poly8_t * p, poly8x16x4_t v) +{ + /* { dg-error "lane 16 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */ + vst4q_lane_p8 (p, v, 16); + /* { dg-error "lane -1 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */ + vst4q_lane_p8 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s16_indices_1.c new file mode 100644 index 00000000000..5fcbc7f03cb --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s16_indices_1.c @@ -0,0 +1,15 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +void +f_vst4q_lane_s16 (int16_t * p, int16x8x4_t v) +{ + /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + vst4q_lane_s16 (p, v, 8); + /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + vst4q_lane_s16 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s32_indices_1.c new file mode 100644 index 00000000000..c039c8729e0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s32_indices_1.c @@ -0,0 +1,15 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +void +f_vst4q_lane_s32 (int32_t * p, int32x4x4_t v) +{ + /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + vst4q_lane_s32 (p, v, 4); + /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + vst4q_lane_s32 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s64_indices_1.c new file mode 100644 index 00000000000..824a7e7e9d0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s64_indices_1.c @@ -0,0 +1,16 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +void +f_vst4q_lane_s64 (int64_t * p, int64x2x4_t v) +{ + /* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */ + vst4q_lane_s64 (p, v, 2); + /* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */ + vst4q_lane_s64 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s8_indices_1.c new file mode 100644 index 00000000000..0850c674d5d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s8_indices_1.c @@ -0,0 +1,16 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +void +f_vst4q_lane_s8 (int8_t * p, int8x16x4_t v) +{ + /* { dg-error "lane 16 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */ + vst4q_lane_s8 (p, v, 16); + /* { dg-error "lane -1 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */ + vst4q_lane_s8 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u16_indices_1.c new file mode 100644 index 00000000000..6950a22921e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u16_indices_1.c @@ -0,0 +1,15 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +void +f_vst4q_lane_u16 (uint16_t * p, uint16x8x4_t v) +{ + /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + vst4q_lane_u16 (p, v, 8); + /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + vst4q_lane_u16 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u32_indices_1.c new file mode 100644 index 00000000000..3c9a1718445 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u32_indices_1.c @@ -0,0 +1,15 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +void +f_vst4q_lane_u32 (uint32_t * p, uint32x4x4_t v) +{ + /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + vst4q_lane_u32 (p, v, 4); + /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + vst4q_lane_u32 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u64_indices_1.c new file mode 100644 index 00000000000..8543e58da00 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u64_indices_1.c @@ -0,0 +1,16 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +void +f_vst4q_lane_u64 (uint64_t * p, uint64x2x4_t v) +{ + /* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */ + vst4q_lane_u64 (p, v, 2); + /* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */ + vst4q_lane_u64 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u8_indices_1.c new file mode 100644 index 00000000000..ade4801600e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u8_indices_1.c @@ -0,0 +1,16 @@ +#include + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +void +f_vst4q_lane_u8 (uint8_t * p, uint8x16x4_t v) +{ + /* { dg-error "lane 16 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */ + vst4q_lane_u8 (p, v, 16); + /* { dg-error "lane -1 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */ + vst4q_lane_u8 (p, v, -1); + return; +} -- 2.30.2