From 4d0ba001d76170cfb2ecf66cb6e01c23b98bae0b Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 28 Mar 2021 18:03:35 +0100 Subject: [PATCH] fix issues with port direction on several pads --- libresoc/core.py | 37 ++++++++++++++++++++----------------- libresoc/ls180.py | 14 +++++++++++--- ls180soc.py | 8 ++++++-- 3 files changed, 37 insertions(+), 22 deletions(-) diff --git a/libresoc/core.py b/libresoc/core.py index cc41a38..3340a0c 100644 --- a/libresoc/core.py +++ b/libresoc/core.py @@ -61,12 +61,14 @@ def make_jtag_ioconn(res, pin, cpupads, iopads): (fn, pin, iotype, pin_name, scan_idx) = pin #serial_tx__core__o, serial_rx__pad__i, # special-case sdram_clock - if pin == 'clock' and fn == 'sdr': - cpu = cpupads['sdram_clock'] - io = iopads['sdram_clock'] - else: - cpu = cpupads[fn] - io = iopads[fn] + #if pin == 'clock' and fn == 'sdr': + # cpu = cpupads['sdram_clock'] + # io = iopads['sdram_clock'] + #else: + # cpu = cpupads[fn] + # io = iopads[fn] + cpu = cpupads[fn] + io = iopads[fn] print ("make_jtag_ioconn", scan_idx) print ("cpupads", cpupads) print ("iopads", iopads) @@ -79,21 +81,22 @@ def make_jtag_ioconn(res, pin, cpupads, iopads): if iotype in (IOType.In, IOType.Out): ps = pin.split("_") - if pin == 'clock' and fn == 'sdr': - cpup = cpu - iop = io - elif len(ps) == 2 and ps[-1].isdigit(): + #if pin == 'clock' and fn == 'sdr': + # cpup = cpu + # iop = io + if len(ps) == 2 and ps[-1].isdigit(): pin, idx = ps idx = int(idx) print ("ps split", pin, idx) cpup = getattr(cpu, pin)[idx] iop = getattr(io, pin)[idx] - elif pin.isdigit(): + elif pin.isdigit() and fn != 'eint': idx = int(pin) print ("digit", idx) cpup = cpu[idx] iop = io[idx] else: + print ("attr", cpu) cpup = getattr(cpu, pin) iop = getattr(io, pin) @@ -328,12 +331,12 @@ class LibreSoC(CPU): litexmap[origperiph] = (periph, num) self.cpupads[origperiph] = self.pad_cm.request(periph, num) iopads[origperiph] = platform.request(periph, num) - if periph == 'sdram': - # special-case sdram clock - ck = self.pad_cm.request("sdram_clock") - self.cpupads['sdram_clock'] = ck - ck = platform.request("sdram_clock") - iopads['sdram_clock'] = ck + #if periph == 'sdram': + # # special-case sdram clock + # ck = self.pad_cm.request("sdram_clock") + # self.cpupads['sdram_clock'] = ck + # ck = platform.request("sdram_clock") + # iopads['sdram_clock'] = ck pinset = get_pinspecs(subset=subset) p = Pins(pinset) diff --git a/libresoc/ls180.py b/libresoc/ls180.py index 8aa40c1..984755d 100644 --- a/libresoc/ls180.py +++ b/libresoc/ls180.py @@ -29,6 +29,13 @@ def make_uart(name, num): Subsignal("rx", Pins("M1"), IOStandard("LVCMOS33")) ) +def make_eint(name, num): + return (name, num, + Subsignal("0", Pins("E0"), IOStandard("LVCMOS33")), + Subsignal("1", Pins("E1"), IOStandard("LVCMOS33")), + Subsignal("2", Pins("E2"), IOStandard("LVCMOS33")), + ) + def make_gpio(name, num, n_gpio): pins = [] for i in range(n_gpio): @@ -103,7 +110,7 @@ def io(): ), # SDRAM: 39 pins - ("sdram_clock", 0, Pins("F19"), IOStandard("LVCMOS33")), + #("sdram_clock", 0, Pins("F19"), IOStandard("LVCMOS33")), ("sdram", 0, Subsignal("a", Pins( "M20 M19 L20 L19 K20 K19 K18 J20", @@ -122,6 +129,7 @@ def io(): Subsignal("cke", Pins("F21")), Subsignal("ba", Pins("P19 N20")), Subsignal("dm", Pins("U19 E20")), + Subsignal("clock", Pins("F19")), IOStandard("LVCMOS33"), Misc("SLEWRATE=FAST"), ), @@ -136,7 +144,7 @@ def io(): _io.append( make_gpio("gpio", 0, n_gpio) ) # EINT: 3 pins - _io.append( ("eint", 0, Pins("E0 E1 E2"), IOStandard("LVCMOS33")) ) + _io.append(make_eint("eint", 0)) # UART0: 2 pins _io.append(make_uart("uart", 0)) @@ -146,7 +154,7 @@ def io(): # not connected - eurgh have to adjust this to match the total pincount. num_nc = 24 num_nc += 4 # mspi1 comments out, litex problems 25mar2021 - #num_nc += 6 # sd0 comments out, litex problems 25mar2021 + num_nc += 6 # sd0 comments out, litex problems 25mar2021 num_nc += 2 # pwm comments out, litex problems 25mar2021 nc = ' '.join("NC%d" % i for i in range(num_nc)) _io.append(("nc", 0, Pins(nc), IOStandard("LVCMOS33"))) diff --git a/ls180soc.py b/ls180soc.py index 0ed93e6..8d2789f 100755 --- a/ls180soc.py +++ b/ls180soc.py @@ -467,7 +467,8 @@ class LibreSoCSim(SoCCore): # SDRAM clock sys_clk = ClockSignal() - sdr_clk = self.cpu.cpupads['sdram_clock'] + #sdr_clk = self.cpu.cpupads['sdram_clock'] + sdr_clk = sdram_pads.clock #self.specials += DDROutput(1, 0, , sdram_clk) self.specials += SDROutput(clk=sys_clk, i=sys_clk, o=sdr_clk) @@ -517,7 +518,10 @@ class LibreSoCSim(SoCCore): # EINTs - very simple, wire up top 3 bits to ls180 "eint" pins eintpads = self.cpu.cpupads['eint'] print ("eintpads", eintpads) - self.comb += self.cpu.interrupt[13:16].eq(eintpads) + self.eint_tmp = Signal(len(eintpads)) + for i in range(len(eintpads)): + self.comb += self.cpu.interrupt[13+i].eq(self.eint_tmp[i]) + self.comb += self.eint_tmp[i].eq(getattr(eintpads, "%d" % i)) # JTAG jtagpads = platform.request("jtag") -- 2.30.2