From 4d1b6da42fabcfd9987ae77056a4bab31780c6e1 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 31 Oct 2014 12:58:36 +0100 Subject: [PATCH] bus/csr: add configurable address_width (needed more than 32 modules with CSR) --- migen/bus/csr.py | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/migen/bus/csr.py b/migen/bus/csr.py index 80ce0fcb..49dc5533 100644 --- a/migen/bus/csr.py +++ b/migen/bus/csr.py @@ -5,16 +5,16 @@ from migen.genlib.record import * from migen.genlib.misc import chooser _layout = [ - ("adr", 14, DIR_M_TO_S), - ("we", 1, DIR_M_TO_S), - ("dat_w", "data_width", DIR_M_TO_S), - ("dat_r", "data_width", DIR_S_TO_M) + ("adr", "address_width", DIR_M_TO_S), + ("we", 1, DIR_M_TO_S), + ("dat_w", "data_width", DIR_M_TO_S), + ("dat_r", "data_width", DIR_S_TO_M) ] class Interface(Record): - def __init__(self, data_width=8): + def __init__(self, data_width=8, address_width=14): Record.__init__(self, set_layout_parameters(_layout, - data_width=data_width)) + data_width=data_width, address_width=address_width)) class Interconnect(Module): def __init__(self, master, slaves): -- 2.30.2