From 4d2a7f511169ed4c7f63189f21f2acc7577da94a Mon Sep 17 00:00:00 2001 From: Anuj Phogat Date: Tue, 24 Mar 2015 16:07:40 -0700 Subject: [PATCH] i965/gen9: Modify the conditions to use blitter on skl+ Conditions modified allow skl+ to use blitter: - for all tiling formats - to write data to YF/YS tiled surfaces Signed-off-by: Anuj Phogat Reviewed-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index 88c0a19bed6..108dd87dd8b 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c @@ -2697,13 +2697,17 @@ use_intel_mipree_map_blit(struct brw_context *brw, { if (brw->has_llc && /* It's probably not worth swapping to the blit ring because of - * all the overhead involved. + * all the overhead involved. But, we must use blitter for the + * surfaces with INTEL_MIPTREE_TRMODE_{YF,YS}. */ - !(mode & GL_MAP_WRITE_BIT) && + (!(mode & GL_MAP_WRITE_BIT) || + mt->tr_mode != INTEL_MIPTREE_TRMODE_NONE) && !mt->compressed && (mt->tiling == I915_TILING_X || /* Prior to Sandybridge, the blitter can't handle Y tiling */ - (brw->gen >= 6 && mt->tiling == I915_TILING_Y)) && + (brw->gen >= 6 && mt->tiling == I915_TILING_Y) || + /* Fast copy blit on skl+ supports all tiling formats. */ + brw->gen >= 9) && can_blit_slice(mt, level, slice)) return true; @@ -2772,6 +2776,8 @@ intel_miptree_map(struct brw_context *brw, intel_miptree_map_movntdqa(brw, mt, map, level, slice); #endif } else { + /* intel_miptree_map_gtt() doesn't support surfaces with Yf/Ys tiling. */ + assert(mt->tr_mode == INTEL_MIPTREE_TRMODE_NONE); intel_miptree_map_gtt(brw, mt, map, level, slice); } -- 2.30.2