From 4d2f8acd2586af5d028fc7e31002d31f25a2e513 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sun, 13 Dec 2020 01:22:21 +0000 Subject: [PATCH] --- openpower/sv/svp_rewrite/svp64/discussion.mdwn | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/openpower/sv/svp_rewrite/svp64/discussion.mdwn b/openpower/sv/svp_rewrite/svp64/discussion.mdwn index 5006b91f9..642375996 100644 --- a/openpower/sv/svp_rewrite/svp64/discussion.mdwn +++ b/openpower/sv/svp_rewrite/svp64/discussion.mdwn @@ -86,13 +86,19 @@ Some examples on different operation widths: 0 1 2 3 4 description ------------------ 0 0 0 0 0 nothing - 0 0 non-zero reserved + 0 0 1 sz dz pred zeroing 0 1 inv CR-bit Rc=1: ffirst CR sel 0 1 inv sz dz Rc=0: ffirst z/nonz 1 0 N sz dz sat mode: N=0/1 u/s - 1 1 0 sz dz pred zeroing - 1 1 1 rsvd reserved + 1 1 inv CR-bit Rc=1: pred-result CR sel + 1 1 inv sz dz Rc=0: pred-result z/nonz +Mode types: + +* **predicate zeroing** (sz, dz) if predication is enabled will put zeros into the dest (or as src in the case of twin pred) when the predicate bit is zero. +* **ffirst* or data-dependent fail-on-first: see separate section. +* **sat mode** or saturation: clamps the result to a min/max rather than overflows / wraps. allows signed and unsigned clamping. +* **pred-result** will test the result (CR testing selects a bit of CR and inverts it, just like branch testing) and if the test fails it is as if the predicate bit was zero. When Rc=1 the CR element (CR0) however is still stored in the CR regfile. This scheme does not apply to crops (crand, cror). # Notes about rounding, clamp and saturate -- 2.30.2