From 4d330f664b590bc6b539745d3d9068cd6b565814 Mon Sep 17 00:00:00 2001
From: =?utf8?q?Jean-Fran=C3=A7ois=20Nguyen?= <jf@lambdaconcept.com>
Date: Mon, 28 Jun 2021 15:47:15 +0200
Subject: [PATCH] =?utf8?q?test:=20=5Fwishbone.py=20=E2=86=92=20utils/wishb?=
 =?utf8?q?one.py?=
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---
 lambdasoc/test/test_periph_base.py                 | 2 +-
 lambdasoc/test/test_periph_serial.py               | 2 +-
 lambdasoc/test/test_periph_sram.py                 | 2 +-
 lambdasoc/test/test_periph_timer.py                | 2 +-
 lambdasoc/test/utils/__init__.py                   | 0
 lambdasoc/test/{_wishbone.py => utils/wishbone.py} | 9 +++++++++
 6 files changed, 13 insertions(+), 4 deletions(-)
 create mode 100644 lambdasoc/test/utils/__init__.py
 rename lambdasoc/test/{_wishbone.py => utils/wishbone.py} (90%)

diff --git a/lambdasoc/test/test_periph_base.py b/lambdasoc/test/test_periph_base.py
index c3f59ff..abd4125 100644
--- a/lambdasoc/test/test_periph_base.py
+++ b/lambdasoc/test/test_periph_base.py
@@ -4,7 +4,7 @@ import unittest
 from nmigen import *
 from nmigen.back.pysim import *
 
-from ._wishbone import *
+from .utils.wishbone import *
 from ..periph.base import Peripheral, CSRBank, PeripheralBridge
 
 
diff --git a/lambdasoc/test/test_periph_serial.py b/lambdasoc/test/test_periph_serial.py
index e73c274..a4a59f0 100644
--- a/lambdasoc/test/test_periph_serial.py
+++ b/lambdasoc/test/test_periph_serial.py
@@ -4,7 +4,7 @@ from nmigen import *
 from nmigen.lib.io import pin_layout
 from nmigen.back.pysim import *
 
-from ._wishbone import *
+from .utils.wishbone import *
 from ..periph.serial import AsyncSerialPeripheral
 
 
diff --git a/lambdasoc/test/test_periph_sram.py b/lambdasoc/test/test_periph_sram.py
index 266de6d..103b3fb 100644
--- a/lambdasoc/test/test_periph_sram.py
+++ b/lambdasoc/test/test_periph_sram.py
@@ -8,7 +8,7 @@ from nmigen.back.pysim import *
 
 from nmigen_soc.wishbone import CycleType, BurstTypeExt
 
-from ._wishbone import *
+from .utils.wishbone import *
 from ..periph.sram import SRAMPeripheral
 
 
diff --git a/lambdasoc/test/test_periph_timer.py b/lambdasoc/test/test_periph_timer.py
index cdbb998..22540f7 100644
--- a/lambdasoc/test/test_periph_timer.py
+++ b/lambdasoc/test/test_periph_timer.py
@@ -5,7 +5,7 @@ import unittest
 from nmigen import *
 from nmigen.back.pysim import *
 
-from ._wishbone import *
+from .utils.wishbone import *
 from ..periph.timer import TimerPeripheral
 
 
diff --git a/lambdasoc/test/utils/__init__.py b/lambdasoc/test/utils/__init__.py
new file mode 100644
index 0000000..e69de29
diff --git a/lambdasoc/test/_wishbone.py b/lambdasoc/test/utils/wishbone.py
similarity index 90%
rename from lambdasoc/test/_wishbone.py
rename to lambdasoc/test/utils/wishbone.py
index c7ab28c..a2eef4a 100644
--- a/lambdasoc/test/_wishbone.py
+++ b/lambdasoc/test/utils/wishbone.py
@@ -1,3 +1,11 @@
+from nmigen import *
+
+from nmigen_soc import wishbone
+
+
+__all__ = ["wb_read", "wb_write"]
+
+
 def wb_read(bus, addr, sel, timeout=32):
     yield bus.cyc.eq(1)
     yield bus.stb.eq(1)
@@ -15,6 +23,7 @@ def wb_read(bus, addr, sel, timeout=32):
     yield bus.stb.eq(0)
     return data
 
+
 def wb_write(bus, addr, data, sel, timeout=32):
     yield bus.cyc.eq(1)
     yield bus.stb.eq(1)
-- 
2.30.2