From 4d56005811887a413604e3c6ea624eb08e074189 Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Sat, 23 Apr 2022 19:49:41 +0100
Subject: [PATCH]

---
 openpower/sv/biginteger.mdwn | 15 ++++++++++++---
 1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/openpower/sv/biginteger.mdwn b/openpower/sv/biginteger.mdwn
index a481f5e21..06ba3ff94 100644
--- a/openpower/sv/biginteger.mdwn
+++ b/openpower/sv/biginteger.mdwn
@@ -34,7 +34,7 @@ Big-Divide.
 Macro-op Fusion and back-end massively-wide SIMD ALUs may be deployed in a
 fashion that is hidden from the user, behind a consistent, stable ISA API.
 
-# Instructions
+# madded
 
 **DRAFT**
 
@@ -74,8 +74,6 @@ When `EXTRA2_MODE` is set to one, the implicit RS register is identical
 to RC extended to SVP64 numbering, including whether RC is set Scalar or
 Vector.
 
-## madded
-
 The pseudocode for `madded RT, RA, RB, RC` is:
 
     prod[0:127] = (RA) * (RB)
@@ -91,3 +89,14 @@ The differences here to `maddhdu` are that `maddhdu` stores the upper
 half in RT, where `madded` stores the upper half in RS. There is no
 equivalent to `maddld` because `maddld` performs sign-extension on RC.
 
+# divqdu RT,EA,RB
+
+Divide Quad-Double Extended Unsigned is an XO-Form instruction
+that is near-identical to `divdeu` except that the lower
+64 bits of the dividend, instead of being zero, contain a second implicit
+register, RS.  RB, the divisor, remains 64 bit.  It is therefore a 128/64
+division, producing a 64 bit result.
+
+Pseudo-code:
+
+    dividend[0:(XLEN*2)-1] <- (RA) || (RS)
-- 
2.30.2