From 4d893c215ef82358c62bfbb44dc4fef57c524df0 Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Wed, 15 Nov 2017 15:27:35 +0000 Subject: [PATCH] arch-arm: Fix MCR/MRC disassemble This patch is fixing the Aarch32 MCR/MRC disassemble, which was previously printing unexisting integer registers as source/destination operands rather than the coprocessor register name Change-Id: I1937938c43680200cf6c5c9558e835ce2b209adc Signed-off-by: Giacomo Travaglini Reviewed-by: Nikos Nikoleris Reviewed-on: https://gem5-review.googlesource.com/5862 Reviewed-by: Jason Lowe-Power Reviewed-by: Andreas Sandberg Maintainer: Andreas Sandberg --- src/arch/arm/insts/misc.cc | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/src/arch/arm/insts/misc.cc b/src/arch/arm/insts/misc.cc index 059f86f63..ec1b9358c 100644 --- a/src/arch/arm/insts/misc.cc +++ b/src/arch/arm/insts/misc.cc @@ -259,10 +259,9 @@ MiscRegRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss); - printIntReg(ss, dest); + printMiscReg(ss, dest); ss << ", "; printIntReg(ss, op1); - ccprintf(ss, ", #%d", imm); return ss.str(); } @@ -273,8 +272,7 @@ RegMiscRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const printMnemonic(ss); printIntReg(ss, dest); ss << ", "; - printIntReg(ss, op1); - ccprintf(ss, ", #%d", imm); + printMiscReg(ss, op1); return ss.str(); } -- 2.30.2