From 4d8a697a3c65aea244334d812afe3567af02d1ca Mon Sep 17 00:00:00 2001 From: Xan Date: Wed, 25 Apr 2018 12:52:48 +0100 Subject: [PATCH] --- ...alysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn b/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn index ca8055d81..61ca490a1 100644 --- a/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn +++ b/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn @@ -2,7 +2,7 @@ Harmonised RVP is a proposal to provide SIMD functionality comparable to the Andes Packed SIMD ISA, but in a manner that is forwards compatible ("harmonised") with the RV Vector specification. -An example use case is a string copy operation - using Harmonised RVP, binary code using integer register based SIMD to copy a string of bytes can also execute (unchanged) on a full RV Vector processor and use the dedicated vector unit to copy string. The is also upwards compatibility between RV32 and RV64 SIMD using this same approach. +An example use case is a string copy operation - using Harmonised RVP, binary code using SIMD instructions operating on integer registers to copy a string can also execute (unchanged) on a full RV Vector processor and use the dedicated vector unit to copy the string. Harmonised RVP also upwards compatibility between RV32 and RV64 SIMD using this same approach. ## Register file comparison -- 2.30.2