From 4d8a7e65660df9e41a061997631763d51dbe2124 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 21 Jul 2020 15:14:00 +0100
Subject: [PATCH] spurious imports of FHDLTestCase, should be from nmutil

---
 src/soc/simulator/test_div_sim.py        | 2 +-
 src/soc/simulator/test_helloworld_sim.py | 2 +-
 src/soc/simulator/test_mul_sim.py        | 2 +-
 src/soc/simulator/test_shift_sim.py      | 2 +-
 src/soc/simulator/test_sim.py            | 2 +-
 src/soc/simulator/test_trap_sim.py       | 2 +-
 6 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/soc/simulator/test_div_sim.py b/src/soc/simulator/test_div_sim.py
index 04278c30..171af5c1 100644
--- a/src/soc/simulator/test_div_sim.py
+++ b/src/soc/simulator/test_div_sim.py
@@ -1,6 +1,6 @@
 from nmigen import Module, Signal
 from nmigen.back.pysim import Simulator, Delay, Settle
-from nmigen.test.utils import FHDLTestCase
+from nmutil.formaltest import FHDLTestCase
 import unittest
 from soc.decoder.power_decoder import (create_pdecode)
 from soc.decoder.power_enums import (Function, MicrOp,
diff --git a/src/soc/simulator/test_helloworld_sim.py b/src/soc/simulator/test_helloworld_sim.py
index 2ff1e006..d1130437 100644
--- a/src/soc/simulator/test_helloworld_sim.py
+++ b/src/soc/simulator/test_helloworld_sim.py
@@ -1,6 +1,6 @@
 from nmigen import Module, Signal
 from nmigen.back.pysim import Simulator, Delay, Settle
-from nmigen.test.utils import FHDLTestCase
+from nmutil.formaltest import FHDLTestCase
 import unittest
 from soc.decoder.power_decoder import (create_pdecode)
 from soc.decoder.power_enums import (Function, MicrOp,
diff --git a/src/soc/simulator/test_mul_sim.py b/src/soc/simulator/test_mul_sim.py
index ef117c3a..6d251056 100644
--- a/src/soc/simulator/test_mul_sim.py
+++ b/src/soc/simulator/test_mul_sim.py
@@ -1,6 +1,6 @@
 from nmigen import Module, Signal
 from nmigen.back.pysim import Simulator, Delay, Settle
-from nmigen.test.utils import FHDLTestCase
+from nmutil.formaltest import FHDLTestCase
 import unittest
 from soc.decoder.power_decoder import (create_pdecode)
 from soc.decoder.power_enums import (Function, MicrOp,
diff --git a/src/soc/simulator/test_shift_sim.py b/src/soc/simulator/test_shift_sim.py
index 3ac85998..e1642105 100644
--- a/src/soc/simulator/test_shift_sim.py
+++ b/src/soc/simulator/test_shift_sim.py
@@ -1,6 +1,6 @@
 from nmigen import Module, Signal
 from nmigen.back.pysim import Simulator, Delay, Settle
-from nmigen.test.utils import FHDLTestCase
+from nmutil.formaltest import FHDLTestCase
 import unittest
 from soc.decoder.power_decoder import (create_pdecode)
 from soc.decoder.power_enums import (Function, MicrOp,
diff --git a/src/soc/simulator/test_sim.py b/src/soc/simulator/test_sim.py
index dae60cea..d6343ae5 100644
--- a/src/soc/simulator/test_sim.py
+++ b/src/soc/simulator/test_sim.py
@@ -1,6 +1,6 @@
 from nmigen import Module, Signal
 from nmigen.back.pysim import Simulator, Delay, Settle
-from nmigen.test.utils import FHDLTestCase
+from nmutil.formaltest import FHDLTestCase
 import unittest
 from soc.decoder.power_decoder import (create_pdecode)
 from soc.decoder.power_enums import (Function, MicrOp,
diff --git a/src/soc/simulator/test_trap_sim.py b/src/soc/simulator/test_trap_sim.py
index d535cf1a..1c794826 100644
--- a/src/soc/simulator/test_trap_sim.py
+++ b/src/soc/simulator/test_trap_sim.py
@@ -1,6 +1,6 @@
 from nmigen import Module, Signal
 from nmigen.back.pysim import Simulator, Delay, Settle
-from nmigen.test.utils import FHDLTestCase
+from nmutil.formaltest import FHDLTestCase
 import unittest
 from soc.decoder.power_decoder import (create_pdecode)
 from soc.decoder.power_enums import (Function, MicrOp,
-- 
2.30.2