From 4d958cd59e98fc30b730e90097d44ab48fa2107c Mon Sep 17 00:00:00 2001 From: Nicolas Robin <13021796+nicolas-robin@users.noreply.github.com> Date: Sun, 15 Mar 2020 10:33:22 +0100 Subject: [PATCH] vendor: fix typo `async_ff_sync` --- nmigen/vendor/xilinx_7series.py | 6 +++--- nmigen/vendor/xilinx_spartan_3_6.py | 6 +++--- nmigen/vendor/xilinx_ultrascale.py | 6 +++--- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/nmigen/vendor/xilinx_7series.py b/nmigen/vendor/xilinx_7series.py index 25bfa28..128035d 100644 --- a/nmigen/vendor/xilinx_7series.py +++ b/nmigen/vendor/xilinx_7series.py @@ -421,12 +421,12 @@ class Xilinx7SeriesPlatform(TemplatedPlatform): m.d.async_ff += o.eq(i) if async_ff_sync._edge == "pos": - m.d.comb += ResetSignal("async_ff").eq(asnyc_ff_sync.i) + m.d.comb += ResetSignal("async_ff").eq(async_ff_sync.i) else: - m.d.comb += ResetSignal("async_ff").eq(~asnyc_ff_sync.i) + m.d.comb += ResetSignal("async_ff").eq(~async_ff_sync.i) m.d.comb += [ - ClockSignal("async_ff").eq(ClockSignal(asnyc_ff_sync._domain)), + ClockSignal("async_ff").eq(ClockSignal(async_ff_sync._domain)), async_ff_sync.o.eq(flops[-1]) ] diff --git a/nmigen/vendor/xilinx_spartan_3_6.py b/nmigen/vendor/xilinx_spartan_3_6.py index c7d37d1..a4b4d99 100644 --- a/nmigen/vendor/xilinx_spartan_3_6.py +++ b/nmigen/vendor/xilinx_spartan_3_6.py @@ -452,12 +452,12 @@ class XilinxSpartan3Or6Platform(TemplatedPlatform): m.d.async_ff += o.eq(i) if async_ff_sync._edge == "pos": - m.d.comb += ResetSignal("async_ff").eq(asnyc_ff_sync.i) + m.d.comb += ResetSignal("async_ff").eq(async_ff_sync.i) else: - m.d.comb += ResetSignal("async_ff").eq(~asnyc_ff_sync.i) + m.d.comb += ResetSignal("async_ff").eq(~async_ff_sync.i) m.d.comb += [ - ClockSignal("async_ff").eq(ClockSignal(asnyc_ff_sync._domain)), + ClockSignal("async_ff").eq(ClockSignal(async_ff_sync._domain)), async_ff_sync.o.eq(flops[-1]) ] diff --git a/nmigen/vendor/xilinx_ultrascale.py b/nmigen/vendor/xilinx_ultrascale.py index 6598f0a..113753c 100644 --- a/nmigen/vendor/xilinx_ultrascale.py +++ b/nmigen/vendor/xilinx_ultrascale.py @@ -417,12 +417,12 @@ class XilinxUltraScalePlatform(TemplatedPlatform): m.d.async_ff += o.eq(i) if async_ff_sync._edge == "pos": - m.d.comb += ResetSignal("async_ff").eq(asnyc_ff_sync.i) + m.d.comb += ResetSignal("async_ff").eq(async_ff_sync.i) else: - m.d.comb += ResetSignal("async_ff").eq(~asnyc_ff_sync.i) + m.d.comb += ResetSignal("async_ff").eq(~async_ff_sync.i) m.d.comb += [ - ClockSignal("async_ff").eq(ClockSignal(asnyc_ff_sync._domain)), + ClockSignal("async_ff").eq(ClockSignal(async_ff_sync._domain)), async_ff_sync.o.eq(flops[-1]) ] -- 2.30.2