From 4dce61c3578a48712315584eba7d9580e4e1b90d Mon Sep 17 00:00:00 2001 From: Staf Verhaegen Date: Fri, 8 May 2020 12:29:45 +0200 Subject: [PATCH] Re: [libre-riscv-dev] minimum viable ASIC --- 21/b20c4511bd36fdf79ac995005e86451f05e0c3 | 82 +++++++++++++++++++++++ 1 file changed, 82 insertions(+) create mode 100644 21/b20c4511bd36fdf79ac995005e86451f05e0c3 diff --git a/21/b20c4511bd36fdf79ac995005e86451f05e0c3 b/21/b20c4511bd36fdf79ac995005e86451f05e0c3 new file mode 100644 index 0000000..74639e6 --- /dev/null +++ b/21/b20c4511bd36fdf79ac995005e86451f05e0c3 @@ -0,0 +1,82 @@ +Return-path: +Envelope-to: publicinbox@libre-riscv.org +Delivery-date: Fri, 08 May 2020 11:29:53 +0100 +Received: from localhost ([::1] helo=libre-riscv.org) + by libre-soc.org with esmtp (Exim 4.89) + (envelope-from ) + id 1jX0GO-0000YM-DI; Fri, 08 May 2020 11:29:52 +0100 +Received: from vps2.stafverhaegen.be ([85.10.201.15]) + by libre-soc.org with esmtp (Exim 4.89) + (envelope-from ) id 1jX0GM-0000YG-Pu + for libre-riscv-dev@lists.libre-riscv.org; Fri, 08 May 2020 11:29:50 +0100 +Received: from hpdc7800 (hpdc7800 [10.0.0.1]) + by vps2.stafverhaegen.be (Postfix) with ESMTP id 23DED11C059A + for ; + Fri, 8 May 2020 12:29:50 +0200 (CEST) +Message-ID: <7fcce2dc2715c268c1029783a83ebcd814c489b9.camel@fibraservi.eu> +From: Staf Verhaegen +To: libre-riscv-dev@lists.libre-riscv.org +Date: Fri, 08 May 2020 12:29:45 +0200 +In-Reply-To: +References: +Organization: FibraServi bvba +X-Mailer: Evolution 3.28.5 (3.28.5-8.el7) +Mime-Version: 1.0 +X-Content-Filtered-By: Mailman/MimeDel 2.1.23 +Subject: Re: [libre-riscv-dev] minimum viable ASIC +X-BeenThere: libre-riscv-dev@lists.libre-riscv.org +X-Mailman-Version: 2.1.23 +Precedence: list +List-Id: Libre-RISCV General Development + +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Reply-To: Libre-RISCV General Development + +Content-Type: multipart/mixed; boundary="===============2823974124656142798==" +Errors-To: libre-riscv-dev-bounces@lists.libre-riscv.org +Sender: "libre-riscv-dev" + + +--===============2823974124656142798== +Content-Type: multipart/signed; micalg="pgp-sha1"; protocol="application/pgp-signature"; + boundary="=-n2C+SGSC3vxgvD5XNQZj" + + +--=-n2C+SGSC3vxgvD5XNQZj +Content-Type: text/plain; charset="UTF-8" +Content-Transfer-Encoding: quoted-printable + +Luke Kenneth Casson Leighton schreef op vr 08-05-2020 om 10:50 [+0100]: +>=20 +> * a PLL (this is quite a lot however it turns the ASIC from a 24mhz +> design into a 300mhz design) + +Why only 24MHz without PLL ? You should have problems getting external +clock frequencies up to 100MHz without a problem inside a chip. + + +--=-n2C+SGSC3vxgvD5XNQZj-- + + + +--===============2823974124656142798== +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: base64 +Content-Disposition: inline + +X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KbGlicmUtcmlz +Y3YtZGV2IG1haWxpbmcgbGlzdApsaWJyZS1yaXNjdi1kZXZAbGlzdHMubGlicmUtcmlzY3Yub3Jn +Cmh0dHA6Ly9saXN0cy5saWJyZS1yaXNjdi5vcmcvbWFpbG1hbi9saXN0aW5mby9saWJyZS1yaXNj +di1kZXYK + +--===============2823974124656142798==-- + + + -- 2.30.2