From 4dec376c237c9ca0330b33047fbad426db31bd21 Mon Sep 17 00:00:00 2001 From: Uros Bizjak Date: Thu, 24 Nov 2016 22:12:19 +0100 Subject: [PATCH] * config/i386/i386.md: Move some more patterns around. From-SVN: r242850 --- gcc/config/i386/i386.md | 212 ++++++++++++++++++++-------------------- 1 file changed, 106 insertions(+), 106 deletions(-) diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 4d7bcfeeccb..5f4cdebfc23 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -8217,6 +8217,18 @@ (const_string "*"))) (set_attr "mode" "SI,DI,DI,SI,DI")]) +;; Turn *anddi_1 into *andsi_1_zext if possible. +(define_split + [(set (match_operand:DI 0 "register_operand") + (and:DI (subreg:DI (match_operand:SI 1 "register_operand") 0) + (match_operand:DI 2 "x86_64_zext_immediate_operand"))) + (clobber (reg:CC FLAGS_REG))] + "TARGET_64BIT" + [(parallel [(set (match_dup 0) + (zero_extend:DI (and:SI (match_dup 1) (match_dup 2)))) + (clobber (reg:CC FLAGS_REG))])] + "operands[2] = gen_lowpart (SImode, operands[2]);") + ;; See comment for addsi_1_zext why we do use nonimmediate_operand (define_insn "*andsi_1_zext" [(set (match_operand:DI 0 "register_operand" "=r") @@ -8338,69 +8350,6 @@ [(set_attr "type" "alu1") (set_attr "mode" "QI")]) -(define_insn "kandn" - [(set (match_operand:SWI12 0 "register_operand" "=r,&r,!k") - (and:SWI12 - (not:SWI12 - (match_operand:SWI12 1 "register_operand" "r,0,k")) - (match_operand:SWI12 2 "register_operand" "r,r,k"))) - (clobber (reg:CC FLAGS_REG))] - "TARGET_AVX512F" -{ - switch (which_alternative) - { - case 0: - return "andn\t{%k2, %k1, %k0|%k0, %k1, %k2}"; - case 1: - return "#"; - case 2: - if (get_attr_mode (insn) == MODE_HI) - return "kandnw\t{%2, %1, %0|%0, %1, %2}"; - else - return "kandn\t{%2, %1, %0|%0, %1, %2}"; - default: - gcc_unreachable (); - } -} - [(set_attr "isa" "bmi,*,avx512f") - (set_attr "type" "bitmanip,*,msklog") - (set_attr "prefix" "*,*,vex") - (set_attr "btver2_decode" "direct,*,*") - (set (attr "mode") - (cond [(and (eq_attr "alternative" "2") - (and (match_test "mode == QImode") - (not (match_test "TARGET_AVX512DQ")))) - (const_string "HI") - ] - (const_string "")))]) - -(define_split - [(set (match_operand:SWI12 0 "general_reg_operand") - (and:SWI12 - (not:SWI12 - (match_dup 0)) - (match_operand:SWI12 1 "general_reg_operand"))) - (clobber (reg:CC FLAGS_REG))] - "TARGET_AVX512F && !TARGET_BMI && reload_completed" - [(set (match_dup 0) - (not:SWI12 (match_dup 0))) - (parallel [(set (match_dup 0) - (and:SWI12 (match_dup 0) - (match_dup 1))) - (clobber (reg:CC FLAGS_REG))])]) - -;; Turn *anddi_1 into *andsi_1_zext if possible. -(define_split - [(set (match_operand:DI 0 "register_operand") - (and:DI (subreg:DI (match_operand:SI 1 "register_operand") 0) - (match_operand:DI 2 "x86_64_zext_immediate_operand"))) - (clobber (reg:CC FLAGS_REG))] - "TARGET_64BIT" - [(parallel [(set (match_dup 0) - (zero_extend:DI (and:SI (match_dup 1) (match_dup 2)))) - (clobber (reg:CC FLAGS_REG))])] - "operands[2] = gen_lowpart (SImode, operands[2]);") - (define_split [(set (match_operand:SWI248 0 "register_operand") (and:SWI248 (match_operand:SWI248 1 "nonimmediate_operand") @@ -8716,6 +8665,100 @@ operands[1] = gen_lowpart (QImode, operands[1]); operands[2] = gen_lowpart (QImode, operands[2]); }) + +(define_insn "kandn" + [(set (match_operand:SWI12 0 "register_operand" "=r,&r,!k") + (and:SWI12 + (not:SWI12 + (match_operand:SWI12 1 "register_operand" "r,0,k")) + (match_operand:SWI12 2 "register_operand" "r,r,k"))) + (clobber (reg:CC FLAGS_REG))] + "TARGET_AVX512F" +{ + switch (which_alternative) + { + case 0: + return "andn\t{%k2, %k1, %k0|%k0, %k1, %k2}"; + case 1: + return "#"; + case 2: + if (get_attr_mode (insn) == MODE_HI) + return "kandnw\t{%2, %1, %0|%0, %1, %2}"; + else + return "kandn\t{%2, %1, %0|%0, %1, %2}"; + default: + gcc_unreachable (); + } +} + [(set_attr "isa" "bmi,*,avx512f") + (set_attr "type" "bitmanip,*,msklog") + (set_attr "prefix" "*,*,vex") + (set_attr "btver2_decode" "direct,*,*") + (set (attr "mode") + (cond [(and (eq_attr "alternative" "2") + (and (match_test "mode == QImode") + (not (match_test "TARGET_AVX512DQ")))) + (const_string "HI") + ] + (const_string "")))]) + +(define_split + [(set (match_operand:SWI12 0 "general_reg_operand") + (and:SWI12 + (not:SWI12 + (match_dup 0)) + (match_operand:SWI12 1 "general_reg_operand"))) + (clobber (reg:CC FLAGS_REG))] + "TARGET_AVX512F && !TARGET_BMI && reload_completed" + [(set (match_dup 0) + (not:SWI12 (match_dup 0))) + (parallel [(set (match_dup 0) + (and:SWI12 (match_dup 0) + (match_dup 1))) + (clobber (reg:CC FLAGS_REG))])]) + +(define_insn_and_split "*andndi3_doubleword" + [(set (match_operand:DI 0 "register_operand" "=r") + (and:DI + (not:DI (match_operand:DI 1 "register_operand" "r")) + (match_operand:DI 2 "nonimmediate_operand" "rm"))) + (clobber (reg:CC FLAGS_REG))] + "TARGET_BMI && !TARGET_64BIT && TARGET_STV && TARGET_SSE" + "#" + "&& reload_completed" + [(parallel [(set (match_dup 0) + (and:SI (not:SI (match_dup 1)) (match_dup 2))) + (clobber (reg:CC FLAGS_REG))]) + (parallel [(set (match_dup 3) + (and:SI (not:SI (match_dup 4)) (match_dup 5))) + (clobber (reg:CC FLAGS_REG))])] + "split_double_mode (DImode, &operands[0], 3, &operands[0], &operands[3]);") + +(define_insn "*bmi_andn_" + [(set (match_operand:SWI48 0 "register_operand" "=r,r") + (and:SWI48 + (not:SWI48 (match_operand:SWI48 1 "register_operand" "r,r")) + (match_operand:SWI48 2 "nonimmediate_operand" "r,m"))) + (clobber (reg:CC FLAGS_REG))] + "TARGET_BMI" + "andn\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "type" "bitmanip") + (set_attr "btver2_decode" "direct, double") + (set_attr "mode" "")]) + +(define_insn "*bmi_andn__ccno" + [(set (reg FLAGS_REG) + (compare + (and:SWI48 + (not:SWI48 (match_operand:SWI48 1 "register_operand" "r,r")) + (match_operand:SWI48 2 "nonimmediate_operand" "r,m")) + (const_int 0))) + (clobber (match_scratch:SWI48 0 "=r,r"))] + "TARGET_BMI && ix86_match_ccmode (insn, CCNOmode)" + "andn\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "type" "bitmanip") + (set_attr "btver2_decode" "direct, double") + (set_attr "mode" "")]) ;; Logical inclusive and exclusive OR instructions @@ -13156,49 +13199,6 @@ ;; BMI instructions. -(define_insn_and_split "*andndi3_doubleword" - [(set (match_operand:DI 0 "register_operand" "=r") - (and:DI - (not:DI (match_operand:DI 1 "register_operand" "r")) - (match_operand:DI 2 "nonimmediate_operand" "rm"))) - (clobber (reg:CC FLAGS_REG))] - "TARGET_BMI && !TARGET_64BIT && TARGET_STV && TARGET_SSE" - "#" - "&& reload_completed" - [(parallel [(set (match_dup 0) - (and:SI (not:SI (match_dup 1)) (match_dup 2))) - (clobber (reg:CC FLAGS_REG))]) - (parallel [(set (match_dup 3) - (and:SI (not:SI (match_dup 4)) (match_dup 5))) - (clobber (reg:CC FLAGS_REG))])] - "split_double_mode (DImode, &operands[0], 3, &operands[0], &operands[3]);") - -(define_insn "*bmi_andn_" - [(set (match_operand:SWI48 0 "register_operand" "=r,r") - (and:SWI48 - (not:SWI48 (match_operand:SWI48 1 "register_operand" "r,r")) - (match_operand:SWI48 2 "nonimmediate_operand" "r,m"))) - (clobber (reg:CC FLAGS_REG))] - "TARGET_BMI" - "andn\t{%2, %1, %0|%0, %1, %2}" - [(set_attr "type" "bitmanip") - (set_attr "btver2_decode" "direct, double") - (set_attr "mode" "")]) - -(define_insn "*bmi_andn__ccno" - [(set (reg FLAGS_REG) - (compare - (and:SWI48 - (not:SWI48 (match_operand:SWI48 1 "register_operand" "r,r")) - (match_operand:SWI48 2 "nonimmediate_operand" "r,m")) - (const_int 0))) - (clobber (match_scratch:SWI48 0 "=r,r"))] - "TARGET_BMI && ix86_match_ccmode (insn, CCNOmode)" - "andn\t{%2, %1, %0|%0, %1, %2}" - [(set_attr "type" "bitmanip") - (set_attr "btver2_decode" "direct, double") - (set_attr "mode" "")]) - (define_insn "bmi_bextr_" [(set (match_operand:SWI48 0 "register_operand" "=r,r") (unspec:SWI48 [(match_operand:SWI48 1 "nonimmediate_operand" "r,m") -- 2.30.2