From 4e0d331d641e8f4648366e4eae09e556b04983b0 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 19 Feb 2020 21:42:20 +0000 Subject: [PATCH] add alu_hier.py example --- examples/alu_hier.py | 63 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) create mode 100644 examples/alu_hier.py diff --git a/examples/alu_hier.py b/examples/alu_hier.py new file mode 100644 index 0000000..4ae6ce4 --- /dev/null +++ b/examples/alu_hier.py @@ -0,0 +1,63 @@ +from nmigen import * +from nmigen.cli import rtlil + + +class Adder(Elaboratable): + def __init__(self, width): + self.a = Signal(width) + self.b = Signal(width) + self.o = Signal(width) + + def elaborate(self, platform): + m = Module() + m.d.comb += self.o.eq(self.a + self.b) + return m + + +class Subtractor(Elaboratable): + def __init__(self, width): + self.a = Signal(width) + self.b = Signal(width) + self.o = Signal(width) + + def elaborate(self, platform): + m = Module() + m.d.comb += self.o.eq(self.a - self.b) + return m + + +class ALU(Elaboratable): + def __init__(self, width): + self.op = Signal() + self.a = Signal(width) + self.b = Signal(width) + self.o = Signal(width) + + self.add = Adder(width) + self.sub = Subtractor(width) + + def elaborate(self, platform): + m = Module() + m.submodules.add = self.add + m.submodules.sub = self.sub + m.d.comb += [ + self.add.a.eq(self.a), + self.sub.a.eq(self.a), + self.add.b.eq(self.b), + self.sub.b.eq(self.b), + ] + with m.If(self.op): + m.d.comb += self.o.eq(self.sub.o) + with m.Else(): + m.d.comb += self.o.eq(self.add.o) + return m + + +def create_ilang(dut, ports, test_name): + vl = rtlil.convert(dut, name=test_name, ports=ports) + with open("%s.il" % test_name, "w") as f: + f.write(vl) + +if __name__ == "__main__": + alu = ALU(width=16) + create_ilang(alu, [alu.op, alu.a, alu.b, alu.o], "alu_hier") -- 2.30.2