From 4e181c8e868230e930292df33f9985c3bb78e30c Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Tue, 3 May 2022 01:05:58 -0700
Subject: [PATCH] fix syntax error

---
 openpower/isa/svfixedarith.mdwn | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/openpower/isa/svfixedarith.mdwn b/openpower/isa/svfixedarith.mdwn
index cd2b320a..7dc9de5e 100644
--- a/openpower/isa/svfixedarith.mdwn
+++ b/openpower/isa/svfixedarith.mdwn
@@ -6,9 +6,9 @@ VA-Form
 
 Pseudo-code:
 
-    <!-- SVP64: RA,RB,RC,RT have EXTRA2, RS as below   -->
-    <!-- bit 8 of EXTRA is clear: RS.[s|v]=RT.[s|v]+VL -->
-    <!-- bit 8 of EXTRA is set  : RS.[s|v]=RC.[s|v]    -->
+    # SVP64: RA,RB,RC,RT have EXTRA2, RS as below
+    # bit 8 of EXTRA is clear: RS.[s|v]=RT.[s|v]+VL
+    # bit 8 of EXTRA is set  : RS.[s|v]=RC.[s|v]
     prod[0:127] <- (RA) * (RB)
     sum[0:127] <- EXTZ(RC) + prod
     RT <- sum[64:127]
@@ -26,9 +26,9 @@ VA-Form
 
 Pseudo-code:
 
-    <!-- SVP64: RA,RB,RC,RT have EXTRA2, RS as below   -->
-    <!-- bit 8 of EXTRA is clear: RS.[s|v]=RT.[s|v]+VL -->
-    <!-- bit 8 of EXTRA is set  : RS.[s|v]=RC.[s|v]    -->
+    # SVP64: RA,RB,RC,RT have EXTRA2, RS as below
+    # bit 8 of EXTRA is clear: RS.[s|v]=RT.[s|v]+VL
+    # bit 8 of EXTRA is set  : RS.[s|v]=RC.[s|v]
     if ((RC) <u (RB)) & ((RB) != [0]*XLEN) then
         dividend[0:(XLEN*2)-1] <- (RC) || (RA)
         divisor[0:(XLEN*2)-1] <- [0]*XLEN || (RB)
-- 
2.30.2