From 4e1d10a3cf3f5ba78b4a3bc4bd96ec60916809b3 Mon Sep 17 00:00:00 2001 From: Nilay Vaish Date: Mon, 9 Mar 2015 09:39:08 -0500 Subject: [PATCH] cpu: o3: commit: mark pipeline delay variable as consts --- src/cpu/o3/commit.hh | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/src/cpu/o3/commit.hh b/src/cpu/o3/commit.hh index a63e8e9e9..6688a70dc 100644 --- a/src/cpu/o3/commit.hh +++ b/src/cpu/o3/commit.hh @@ -406,29 +406,29 @@ class DefaultCommit std::list priority_list; /** IEW to Commit delay. */ - Cycles iewToCommitDelay; + const Cycles iewToCommitDelay; /** Commit to IEW delay. */ - Cycles commitToIEWDelay; + const Cycles commitToIEWDelay; /** Rename to ROB delay. */ - Cycles renameToROBDelay; + const Cycles renameToROBDelay; - Cycles fetchToCommitDelay; + const Cycles fetchToCommitDelay; /** Rename width, in instructions. Used so ROB knows how many * instructions to get from the rename instruction queue. */ - unsigned renameWidth; + const unsigned renameWidth; /** Commit width, in instructions. */ - unsigned commitWidth; + const unsigned commitWidth; /** Number of Reorder Buffers */ unsigned numRobs; /** Number of Active Threads */ - ThreadID numThreads; + const ThreadID numThreads; /** Is a drain pending? Commit is looking for an instruction boundary while * there are no pending interrupts @@ -445,7 +445,7 @@ class DefaultCommit /** The latency to handle a trap. Used when scheduling trap * squash event. */ - Cycles trapLatency; + const Cycles trapLatency; /** The interrupt fault. */ Fault interrupt; -- 2.30.2