From 4e618f75f69ea4a8796907848d7aec4e37b93c56 Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Tue, 26 Sep 2023 21:39:31 -0700 Subject: [PATCH] log writing CA[32]/OV[32] for OP_ADD --- src/openpower/decoder/isa/caller.py | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py index eaf0af47..c070337b 100644 --- a/src/openpower/decoder/isa/caller.py +++ b/src/openpower/decoder/isa/caller.py @@ -1535,10 +1535,14 @@ class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop): # TODO: if 32-bit mode, set ov to ov32 self.spr['XER'][XER_bits['OV']] = ov self.spr['XER'][XER_bits['OV32']] = ov32 + log(f"write OV/OV32 OV={ov} OV32={ov32}", + kind=LogKind.InstrInOuts) else: # TODO: if 32-bit mode, set ca to ca32 self.spr['XER'][XER_bits['CA']] = ca self.spr['XER'][XER_bits['CA32']] = ca32 + log(f"write CA/CA32 CA={ca} CA32={ca32}", + kind=LogKind.InstrInOuts) return inv_a = yield self.dec2.e.do.invert_in if inv_a: -- 2.30.2