From 4e6d03ed96b7c6a2d390fd51b7baae1bfded832e Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 4 Oct 2018 15:38:52 +0100 Subject: [PATCH] add twin-predicated sv c_mv unit test (no zeroing) --- isa/macros/simplev/sv_test_macros.h | 4 ++ isa/rv64uc/Makefrag.sv | 1 + isa/rv64uc/sv_c_mv_predication.S | 90 +++++++++++++++++++++++++++++ 3 files changed, 95 insertions(+) create mode 100644 isa/rv64uc/sv_c_mv_predication.S diff --git a/isa/macros/simplev/sv_test_macros.h b/isa/macros/simplev/sv_test_macros.h index 23feaa1..421d0c3 100644 --- a/isa/macros/simplev/sv_test_macros.h +++ b/isa/macros/simplev/sv_test_macros.h @@ -16,6 +16,10 @@ li x1, c1 | ((c2)<<16); \ csrrw x0, 0x4c0, x1 +#define SET_SV_2PREDCSRS( c1, c2 ) \ + li x1, c1 | ((c2)<<16); \ + csrrw x0, 0x4c8, x1 + #define CLR_SV_CSRS( ) csrrw x0, 0x4c0, 0 #define CLR_SV_PRED_CSRS( ) csrrw x0, 0x4c8, 0 diff --git a/isa/rv64uc/Makefrag.sv b/isa/rv64uc/Makefrag.sv index e35fb34..ebd293c 100644 --- a/isa/rv64uc/Makefrag.sv +++ b/isa/rv64uc/Makefrag.sv @@ -4,6 +4,7 @@ rv64uc_sv_tests = \ sv_c_mv \ + sv_c_mv_predication \ rv64uc_p_tests = $(addprefix rv64uc-p-, $(rv64uc_sv_tests)) rv64uc_v_tests = $(addprefix rv64uc-v-, $(rv64uc_sv_tests)) diff --git a/isa/rv64uc/sv_c_mv_predication.S b/isa/rv64uc/sv_c_mv_predication.S new file mode 100644 index 0000000..65b2bd6 --- /dev/null +++ b/isa/rv64uc/sv_c_mv_predication.S @@ -0,0 +1,90 @@ +#include "riscv_test.h" +#include "sv_test_macros.h" + +RVTEST_RV64U # Define TVM used by program. + + +#define SV_PRED_C_MV_TEST( pred1, pred2, expect1, expect2, expect3 ) \ + \ + SV_LD_DATA( x5, testdata+0 , 0); \ + SV_LD_DATA( x6, testdata+8, 0); \ + SV_LD_DATA( x7, testdata+16, 0); \ + \ + li x2, 2; \ + li x3, 3; \ + li x4, 4; \ + li a3, pred1; \ + li a4, pred2; \ + \ + SET_SV_MVL(3); \ + SET_SV_2CSRS( SV_REG_CSR(1, 2, 0, 2, 1, 0), \ + SV_REG_CSR(1, 5, 0, 5, 1, 0) ); \ + SET_SV_2PREDCSRS( \ + SV_PRED_CSR(1, 2, 0, 0, 13, 1), \ + SV_PRED_CSR(1, 5, 0, 0, 14, 1) );\ + SET_SV_VL(3); \ + \ + .option rvc; \ + c.mv x2, x5; \ + .option norvc; \ + \ + SET_SV_VL(0); \ + CLR_SV_CSRS(); \ + SET_SV_MVL(0); \ + \ + TEST_SV_IMM(x2, expect1); \ + TEST_SV_IMM(x3, expect2); \ + TEST_SV_IMM(x4, expect3); + +# SV test: vector-vector add different rd and rs1 +# +# sets up x6 and x7 with data, sets VL to 2, and carries out +# an "x3 = 1 + x6". which actually means "x3 = 1 + x6 *AND* x4 = 1 + x7" + +# Test code region. +RVTEST_CODE_BEGIN # Start of test code. + + .option norvc + + SV_PRED_C_MV_TEST( 0x7, 0x7, 1001, 41, 42 ) + SV_PRED_C_MV_TEST( 0x3, 0x7, 1001, 41, 4 ) + SV_PRED_C_MV_TEST( 0x1, 0x7, 1001, 3, 4 ) + + SV_PRED_C_MV_TEST( 0x6, 0x7, 2, 1001, 41 ) + SV_PRED_C_MV_TEST( 0x6, 0x3, 2, 1001, 41 ) + SV_PRED_C_MV_TEST( 0x6, 0x1, 2, 1001, 4 ) + SV_PRED_C_MV_TEST( 0x6, 0x6, 2, 41, 42 ) + + SV_PRED_C_MV_TEST( 0x5, 0x6, 41, 3, 42 ) + + SV_PRED_C_MV_TEST( 0x1, 0x1, 1001, 3, 4 ) + SV_PRED_C_MV_TEST( 0x2, 0x1, 2, 1001, 4 ) + SV_PRED_C_MV_TEST( 0x4, 0x1, 2, 3, 1001 ) + + SV_PRED_C_MV_TEST( 0x1, 0x1, 1001, 3, 4 ) + SV_PRED_C_MV_TEST( 0x1, 0x2, 41, 3, 4 ) + SV_PRED_C_MV_TEST( 0x1, 0x4, 42, 3, 4 ) + + RVTEST_PASS # Signal success. +fail: + RVTEST_FAIL +RVTEST_CODE_END # End of test code. + +# Input data section. +# This section is optional, and this data is NOT saved in the output. +.data + .align 3 +testdata: + .dword 1001 + .dword 41 + .dword 42 + +# Output data section. +RVTEST_DATA_BEGIN # Start of test output data region. + .align 3 +result: + .dword -1 + .dword -1 + .dword -1 +RVTEST_DATA_END # End of test output data region. + -- 2.30.2