From 4e708f5ebd82ce7e63d7f6ba43fde3b921c0fe53 Mon Sep 17 00:00:00 2001 From: Kewen Lin Date: Wed, 7 Aug 2019 07:11:14 +0000 Subject: [PATCH] rs6000: support vector int type rotatert gcc/ChangeLog 2019-08-07 Kewen Lin * config/rs6000/vector.md (vrotr3): New define_expand. gcc/testsuite/ChangeLog 2019-08-07 Kewen Lin * gcc.target/powerpc/vec_rotate-1.c: New test. * gcc.target/powerpc/vec_rotate-2.c: New test. * gcc.target/powerpc/vec_rotate-3.c: New test. * gcc.target/powerpc/vec_rotate-4.c: New test. From-SVN: r274158 --- gcc/ChangeLog | 4 ++ gcc/config/rs6000/vector.md | 13 ++++++ gcc/testsuite/ChangeLog | 7 ++++ .../gcc.target/powerpc/vec_rotate-1.c | 39 ++++++++++++++++++ .../gcc.target/powerpc/vec_rotate-2.c | 18 +++++++++ .../gcc.target/powerpc/vec_rotate-3.c | 40 +++++++++++++++++++ .../gcc.target/powerpc/vec_rotate-4.c | 19 +++++++++ 7 files changed, 140 insertions(+) create mode 100644 gcc/testsuite/gcc.target/powerpc/vec_rotate-1.c create mode 100644 gcc/testsuite/gcc.target/powerpc/vec_rotate-2.c create mode 100644 gcc/testsuite/gcc.target/powerpc/vec_rotate-3.c create mode 100644 gcc/testsuite/gcc.target/powerpc/vec_rotate-4.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 0fc0a212888..b85a1dba105 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,7 @@ +2019-08-07 Kewen Lin + + * config/rs6000/vector.md (vrotr3): New define_expand. + 2019-08-07 Kito Cheng * gcc/config/riscv/multilib-generator: (canonical_order): Add 'g'. diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md index 70bcfe02e22..886cbad1655 100644 --- a/gcc/config/rs6000/vector.md +++ b/gcc/config/rs6000/vector.md @@ -1260,6 +1260,19 @@ "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)" "") +;; Expanders for rotatert to make use of vrotl +(define_expand "vrotr3" + [(set (match_operand:VEC_I 0 "vint_operand") + (rotatert:VEC_I (match_operand:VEC_I 1 "vint_operand") + (match_operand:VEC_I 2 "vint_operand")))] + "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)" +{ + rtx rot_count = gen_reg_rtx (mode); + emit_insn (gen_neg2 (rot_count, operands[2])); + emit_insn (gen_vrotl3 (operands[0], operands[1], rot_count)); + DONE; +}) + ;; Expanders for arithmetic shift left on each vector element (define_expand "vashl3" [(set (match_operand:VEC_I 0 "vint_operand") diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index d7eda8e784e..a372d7fbcf1 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,10 @@ +2019-08-07 Kewen Lin + + * gcc.target/powerpc/vec_rotate-1.c: New test. + * gcc.target/powerpc/vec_rotate-2.c: New test. + * gcc.target/powerpc/vec_rotate-3.c: New test. + * gcc.target/powerpc/vec_rotate-4.c: New test. + 2019-08-07 Alexandre Oliva * gcc.target/i386/math_m_pi.h: New. diff --git a/gcc/testsuite/gcc.target/powerpc/vec_rotate-1.c b/gcc/testsuite/gcc.target/powerpc/vec_rotate-1.c new file mode 100644 index 00000000000..f035a578292 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vec_rotate-1.c @@ -0,0 +1,39 @@ +/* { dg-options "-O3" } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ + +/* Check vectorizer can exploit vector rotation instructions on Power, mainly + for the case rotation count is const number. + + Check for instructions vrlb/vrlh/vrlw only available if altivec supported. */ + +#define N 256 +unsigned int suw[N], ruw[N]; +unsigned short suh[N], ruh[N]; +unsigned char sub[N], rub[N]; + +void +testUW () +{ + for (int i = 0; i < 256; ++i) + ruw[i] = (suw[i] >> 8) | (suw[i] << (sizeof (suw[0]) * 8 - 8)); +} + +void +testUH () +{ + for (int i = 0; i < 256; ++i) + ruh[i] = (unsigned short) (suh[i] >> 9) + | (unsigned short) (suh[i] << (sizeof (suh[0]) * 8 - 9)); +} + +void +testUB () +{ + for (int i = 0; i < 256; ++i) + rub[i] = (unsigned char) (sub[i] >> 5) + | (unsigned char) (sub[i] << (sizeof (sub[0]) * 8 - 5)); +} + +/* { dg-final { scan-assembler {\mvrlw\M} } } */ +/* { dg-final { scan-assembler {\mvrlh\M} } } */ +/* { dg-final { scan-assembler {\mvrlb\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec_rotate-2.c b/gcc/testsuite/gcc.target/powerpc/vec_rotate-2.c new file mode 100644 index 00000000000..23598958ef2 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vec_rotate-2.c @@ -0,0 +1,18 @@ +/* { dg-options "-O3 -mdejagnu-cpu=power8" } */ + +/* Check vectorizer can exploit vector rotation instructions on Power8, mainly + for the case rotation count is const number. + + Check for vrld which is available on Power8 and above. */ + +#define N 256 +unsigned long long sud[N], rud[N]; + +void +testULL () +{ + for (int i = 0; i < 256; ++i) + rud[i] = (sud[i] >> 8) | (sud[i] << (sizeof (sud[0]) * 8 - 8)); +} + +/* { dg-final { scan-assembler {\mvrld\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec_rotate-3.c b/gcc/testsuite/gcc.target/powerpc/vec_rotate-3.c new file mode 100644 index 00000000000..5e90ae6fd63 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vec_rotate-3.c @@ -0,0 +1,40 @@ +/* { dg-options "-O3" } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ + +/* Check vectorizer can exploit vector rotation instructions on Power, mainly + for the case rotation count isn't const number. + + Check for instructions vrlb/vrlh/vrlw only available if altivec supported. */ + +#define N 256 +unsigned int suw[N], ruw[N]; +unsigned short suh[N], ruh[N]; +unsigned char sub[N], rub[N]; +extern unsigned char rot_cnt; + +void +testUW () +{ + for (int i = 0; i < 256; ++i) + ruw[i] = (suw[i] >> rot_cnt) | (suw[i] << (sizeof (suw[0]) * 8 - rot_cnt)); +} + +void +testUH () +{ + for (int i = 0; i < 256; ++i) + ruh[i] = (unsigned short) (suh[i] >> rot_cnt) + | (unsigned short) (suh[i] << (sizeof (suh[0]) * 8 - rot_cnt)); +} + +void +testUB () +{ + for (int i = 0; i < 256; ++i) + rub[i] = (unsigned char) (sub[i] >> rot_cnt) + | (unsigned char) (sub[i] << (sizeof (sub[0]) * 8 - rot_cnt)); +} + +/* { dg-final { scan-assembler {\mvrlw\M} } } */ +/* { dg-final { scan-assembler {\mvrlh\M} } } */ +/* { dg-final { scan-assembler {\mvrlb\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec_rotate-4.c b/gcc/testsuite/gcc.target/powerpc/vec_rotate-4.c new file mode 100644 index 00000000000..75f08f07ba7 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vec_rotate-4.c @@ -0,0 +1,19 @@ +/* { dg-options "-O3 -mdejagnu-cpu=power8" } */ + +/* Check vectorizer can exploit vector rotation instructions on Power8, mainly + for the case rotation count isn't const number. + + Check for vrld which is available on Power8 and above. */ + +#define N 256 +unsigned long long sud[N], rud[N]; +extern unsigned char rot_cnt; + +void +testULL () +{ + for (int i = 0; i < 256; ++i) + rud[i] = (sud[i] >> rot_cnt) | (sud[i] << (sizeof (sud[0]) * 8 - rot_cnt)); +} + +/* { dg-final { scan-assembler {\mvrld\M} } } */ -- 2.30.2