From 4e72bd821391cf495f72084c44cd9ec796ca9b1b Mon Sep 17 00:00:00 2001
From: programmerjake <programmerjake@web>
Date: Wed, 2 Feb 2022 12:48:39 +0000
Subject: [PATCH] add reason to prefer one reduce pseudo-code over the other

---
 openpower/sv/svp64/appendix.mdwn | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn
index 3e626caaa..fca8502d4 100644
--- a/openpower/sv/svp64/appendix.mdwn
+++ b/openpower/sv/svp64/appendix.mdwn
@@ -720,7 +720,7 @@ For modes:
 /// `temp_pred` is a user-visible Vector Condition register 
 ///
 /// all input arrays have length `vl`
-def reduce(  vl,  vec, pred, pred,):
+def reduce(vl, vec, pred):
     step = 1;
     while step < vl
         step *= 2;
@@ -732,7 +732,13 @@ def reduce(  vl,  vec, pred, pred,):
             else if other_pred
                 vec[i] = vec[other];
             pred[i] |= other_pred;
+```
 
+we'd want to use something based on the above pseudo-code
+rather than the below pseudo-code -- reasoning here:
+<https://bugs.libre-soc.org/show_bug.cgi?id=697#c11>
+
+```
 def reduce(  vl,  vec, pred, pred,):
     j = 0
     vi = [] # array of lookup indices to skip nonpredicated
-- 
2.30.2