From 4e9a8ffe9ca542d0c58e6cc408ce646525e4f856 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 20 Mar 2020 22:02:36 +0100 Subject: [PATCH] targets: switch to SoCCore/add_sdram instead of SoCSDRAM. --- litex/boards/targets/arty.py | 20 +++++++++++++------- litex/boards/targets/de0nano.py | 20 +++++++++++++------- litex/boards/targets/genesys2.py | 20 +++++++++++++------- litex/boards/targets/kc705.py | 20 +++++++++++++------- litex/boards/targets/kcu105.py | 20 +++++++++++++------- litex/boards/targets/minispartan6.py | 20 +++++++++++++------- litex/boards/targets/netv2.py | 20 +++++++++++++------- litex/boards/targets/nexys_video.py | 20 +++++++++++++------- litex/boards/targets/pcie_screamer.py | 20 +++++++++++++------- litex/boards/targets/ulx3s.py | 21 ++++++++++++++------- litex/boards/targets/versa_ecp5.py | 14 ++++++++++---- 11 files changed, 141 insertions(+), 74 deletions(-) diff --git a/litex/boards/targets/arty.py b/litex/boards/targets/arty.py index b7f36b30..41e306fe 100755 --- a/litex/boards/targets/arty.py +++ b/litex/boards/targets/arty.py @@ -11,6 +11,7 @@ from litex.boards.platforms import arty from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict from litex.soc.cores.clock import * +from litex.soc.integration.soc_core import * from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * @@ -51,12 +52,12 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ -class BaseSoC(SoCSDRAM): +class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(100e6), **kwargs): platform = arty.Platform() - # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + # SoCCore ---------------------------------------------------------------------------------- + SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) @@ -69,10 +70,15 @@ class BaseSoC(SoCSDRAM): sys_clk_freq = sys_clk_freq, interface_type = "MEMORY") self.add_csr("ddrphy") - sdram_module = MT41K128M16(sys_clk_freq, "1:4") - self.register_sdram(self.ddrphy, - geom_settings = sdram_module.geom_settings, - timing_settings = sdram_module.timing_settings) + self.add_sdram("sdram", + phy = self.ddrphy, + module = MT41K128M16(sys_clk_freq, "1:4"), + origin = self.mem_map["main_ram"], + size = kwargs.get("max_sdram_size", 0x40000000), + l2_cache_size = kwargs.get("l2_size", 8192), + l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), + l2_cache_reverse = True + ) # EthernetSoC -------------------------------------------------------------------------------------- diff --git a/litex/boards/targets/de0nano.py b/litex/boards/targets/de0nano.py index b9385f2d..d6d059f7 100755 --- a/litex/boards/targets/de0nano.py +++ b/litex/boards/targets/de0nano.py @@ -10,6 +10,7 @@ from migen.genlib.resetsync import AsyncResetSynchronizer from litex_boards.platforms import de0nano +from litex.soc.integration.soc_core import * from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * @@ -70,13 +71,13 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ -class BaseSoC(SoCSDRAM): +class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(50e6), **kwargs): assert sys_clk_freq == int(50e6) platform = de0nano.Platform() - # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + # SoCCore ---------------------------------------------------------------------------------- + SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform) @@ -84,10 +85,15 @@ class BaseSoC(SoCSDRAM): # SDR SDRAM -------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) - sdram_module = IS42S16160(self.clk_freq, "1:1") - self.register_sdram(self.sdrphy, - geom_settings = sdram_module.geom_settings, - timing_settings = sdram_module.timing_settings) + self.add_sdram("sdram", + phy = self.sdrphy, + module = IS42S16160(self.clk_freq, "1:1"), + origin = self.mem_map["main_ram"], + size = kwargs.get("max_sdram_size", 0x40000000), + l2_cache_size = kwargs.get("l2_size", 8192), + l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), + l2_cache_reverse = True + ) # Build -------------------------------------------------------------------------------------------- diff --git a/litex/boards/targets/genesys2.py b/litex/boards/targets/genesys2.py index 583176cd..c8ddcde6 100755 --- a/litex/boards/targets/genesys2.py +++ b/litex/boards/targets/genesys2.py @@ -10,6 +10,7 @@ from migen import * from litex.boards.platforms import genesys2 from litex.soc.cores.clock import * +from litex.soc.integration.soc_core import * from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * @@ -42,12 +43,12 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ -class BaseSoC(SoCSDRAM): +class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(125e6), **kwargs): platform = genesys2.Platform() - # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + # SoCCore ---------------------------------------------------------------------------------- + SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) @@ -59,10 +60,15 @@ class BaseSoC(SoCSDRAM): nphases = 4, sys_clk_freq = sys_clk_freq) self.add_csr("ddrphy") - sdram_module = MT41J256M16(self.clk_freq, "1:4") - self.register_sdram(self.ddrphy, - geom_settings = sdram_module.geom_settings, - timing_settings = sdram_module.timing_settings) + self.add_sdram("sdram", + phy = self.ddrphy, + module = MT41J256M16(self.clk_freq, "1:4"), + origin = self.mem_map["main_ram"], + size = kwargs.get("max_sdram_size", 0x40000000), + l2_cache_size = kwargs.get("l2_size", 8192), + l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), + l2_cache_reverse = True + ) # EthernetSoC -------------------------------------------------------------------------------------- diff --git a/litex/boards/targets/kc705.py b/litex/boards/targets/kc705.py index 874f39ab..3c6d2374 100755 --- a/litex/boards/targets/kc705.py +++ b/litex/boards/targets/kc705.py @@ -12,6 +12,7 @@ from migen import * from litex.boards.platforms import kc705 from litex.soc.cores.clock import * +from litex.soc.integration.soc_core import * from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * @@ -42,12 +43,12 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ -class BaseSoC(SoCSDRAM): +class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(125e6), **kwargs): platform = kc705.Platform() - # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + # SoCCore ---------------------------------------------------------------------------------- + SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) @@ -61,10 +62,15 @@ class BaseSoC(SoCSDRAM): cmd_latency = 1) self.add_csr("ddrphy") self.add_constant("DDRPHY_CMD_DELAY", 13) - sdram_module = MT8JTF12864(sys_clk_freq, "1:4") - self.register_sdram(self.ddrphy, - geom_settings = sdram_module.geom_settings, - timing_settings = sdram_module.timing_settings) + self.add_sdram("sdram", + phy = self.ddrphy, + module = MT8JTF12864(sys_clk_freq, "1:4"), + origin = self.mem_map["main_ram"], + size = kwargs.get("max_sdram_size", 0x40000000), + l2_cache_size = kwargs.get("l2_size", 8192), + l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), + l2_cache_reverse = True + ) # EthernetSoC -------------------------------------------------------------------------------------- diff --git a/litex/boards/targets/kcu105.py b/litex/boards/targets/kcu105.py index 8f2cec69..12693dd5 100755 --- a/litex/boards/targets/kcu105.py +++ b/litex/boards/targets/kcu105.py @@ -10,6 +10,7 @@ from migen import * from litex.boards.platforms import kcu105 from litex.soc.cores.clock import * +from litex.soc.integration.soc_core import * from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * @@ -49,12 +50,12 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ -class BaseSoC(SoCSDRAM): +class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(125e6), **kwargs): platform = kcu105.Platform() - # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + # SoCCore ---------------------------------------------------------------------------------- + SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) @@ -68,10 +69,15 @@ class BaseSoC(SoCSDRAM): cmd_latency = 0) self.add_csr("ddrphy") self.add_constant("USDDRPHY", None) - sdram_module = EDY4016A(sys_clk_freq, "1:4") - self.register_sdram(self.ddrphy, - geom_settings = sdram_module.geom_settings, - timing_settings = sdram_module.timing_settings) + self.add_sdram("sdram", + phy = self.ddrphy, + module = EDY4016A(sys_clk_freq, "1:4"), + origin = self.mem_map["main_ram"], + size = kwargs.get("max_sdram_size", 0x40000000), + l2_cache_size = kwargs.get("l2_size", 8192), + l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), + l2_cache_reverse = True + ) # EthernetSoC -------------------------------------------------------------------------------------- diff --git a/litex/boards/targets/minispartan6.py b/litex/boards/targets/minispartan6.py index e67c16da..00d68793 100755 --- a/litex/boards/targets/minispartan6.py +++ b/litex/boards/targets/minispartan6.py @@ -14,6 +14,7 @@ from migen.genlib.resetsync import AsyncResetSynchronizer from litex.boards.platforms import minispartan6 from litex.soc.cores.clock import * +from litex.soc.integration.soc_core import * from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * @@ -43,13 +44,13 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ -class BaseSoC(SoCSDRAM): +class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(80e6), **kwargs): assert sys_clk_freq == int(80e6) platform = minispartan6.Platform() - # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + # SoCCore ---------------------------------------------------------------------------------- + SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) @@ -57,10 +58,15 @@ class BaseSoC(SoCSDRAM): # SDR SDRAM -------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) - sdram_module = AS4C16M16(sys_clk_freq, "1:1") - self.register_sdram(self.sdrphy, - geom_settings = sdram_module.geom_settings, - timing_settings = sdram_module.timing_settings) + self.add_sdram("sdram", + phy = self.sdrphy, + module = AS4C16M16(sys_clk_freq, "1:1"), + origin = self.mem_map["main_ram"], + size = kwargs.get("max_sdram_size", 0x40000000), + l2_cache_size = kwargs.get("l2_size", 8192), + l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), + l2_cache_reverse = True + ) # Build -------------------------------------------------------------------------------------------- diff --git a/litex/boards/targets/netv2.py b/litex/boards/targets/netv2.py index fb6e150f..e066d0f0 100755 --- a/litex/boards/targets/netv2.py +++ b/litex/boards/targets/netv2.py @@ -10,6 +10,7 @@ from migen import * from litex.boards.platforms import netv2 from litex.soc.cores.clock import * +from litex.soc.integration.soc_core import * from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * @@ -45,12 +46,12 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ -class BaseSoC(SoCSDRAM): +class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(100e6), **kwargs): platform = netv2.Platform() - # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + # SoCCore --------------------------------------------------------------------------------- + SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) @@ -62,10 +63,15 @@ class BaseSoC(SoCSDRAM): nphases = 4, sys_clk_freq = sys_clk_freq) self.add_csr("ddrphy") - sdram_module = K4B2G1646F(sys_clk_freq, "1:4") - self.register_sdram(self.ddrphy, - geom_settings = sdram_module.geom_settings, - timing_settings = sdram_module.timing_settings) + self.add_sdram("sdram", + phy = self.ddrphy, + module = K4B2G1646F(sys_clk_freq, "1:4"), + origin = self.mem_map["main_ram"], + size = kwargs.get("max_sdram_size", 0x40000000), + l2_cache_size = kwargs.get("l2_size", 8192), + l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), + l2_cache_reverse = True + ) # EthernetSoC -------------------------------------------------------------------------------------- diff --git a/litex/boards/targets/nexys_video.py b/litex/boards/targets/nexys_video.py index 9773f9ac..e3d9f4b3 100755 --- a/litex/boards/targets/nexys_video.py +++ b/litex/boards/targets/nexys_video.py @@ -10,6 +10,7 @@ from migen import * from litex.boards.platforms import nexys_video from litex.soc.cores.clock import * +from litex.soc.integration.soc_core import * from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * @@ -44,12 +45,12 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ -class BaseSoC(SoCSDRAM): +class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(100e6), **kwargs): platform = nexys_video.Platform() - # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + # SoCCore ---------------------------------------------------------------------------------- + SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) @@ -61,10 +62,15 @@ class BaseSoC(SoCSDRAM): nphases = 4, sys_clk_freq = sys_clk_freq) self.add_csr("ddrphy") - sdram_module = MT41K256M16(sys_clk_freq, "1:4") - self.register_sdram(self.ddrphy, - geom_settings = sdram_module.geom_settings, - timing_settings = sdram_module.timing_settings) + self.add_sdram("sdram", + phy = self.ddrphy, + module = MT41K256M16(sys_clk_freq, "1:4"), + origin = self.mem_map["main_ram"], + size = kwargs.get("max_sdram_size", 0x40000000), + l2_cache_size = kwargs.get("l2_size", 8192), + l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), + l2_cache_reverse = True + ) # EthernetSoC -------------------------------------------------------------------------------------- diff --git a/litex/boards/targets/pcie_screamer.py b/litex/boards/targets/pcie_screamer.py index f94d40fe..2dfb1644 100755 --- a/litex/boards/targets/pcie_screamer.py +++ b/litex/boards/targets/pcie_screamer.py @@ -11,6 +11,7 @@ from litex.boards.platforms import pcie_screamer from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict from litex.soc.cores.clock import * +from litex.soc.integration.soc_core import * from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * @@ -38,12 +39,12 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ -class BaseSoC(SoCSDRAM): +class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(100e6), **kwargs): platform = pcie_screamer.Platform() - # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + # SoCCore ---------------------------------------------------------------------------------- + SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) @@ -55,10 +56,15 @@ class BaseSoC(SoCSDRAM): nphases = 4, sys_clk_freq = sys_clk_freq) self.add_csr("ddrphy") - sdram_module = MT41K128M16(sys_clk_freq, "1:4") - self.register_sdram(self.ddrphy, - geom_settings = sdram_module.geom_settings, - timing_settings = sdram_module.timing_settings) + self.add_sdram("sdram", + phy = self.ddrphy, + module = MT41K128M16(sys_clk_freq, "1:4"), + origin = self.mem_map["main_ram"], + size = kwargs.get("max_sdram_size", 0x40000000), + l2_cache_size = kwargs.get("l2_size", 8192), + l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), + l2_cache_reverse = True + ) # Build -------------------------------------------------------------------------------------------- diff --git a/litex/boards/targets/ulx3s.py b/litex/boards/targets/ulx3s.py index ee641e66..ce0ddcdb 100755 --- a/litex/boards/targets/ulx3s.py +++ b/litex/boards/targets/ulx3s.py @@ -15,6 +15,7 @@ from litex_boards.platforms import ulx3s from litex.build.lattice.trellis import trellis_args, trellis_argdict from litex.soc.cores.clock import * +from litex.soc.integration.soc_core import * from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * @@ -51,13 +52,14 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ -class BaseSoC(SoCSDRAM): +class BaseSoC(SoCCore): def __init__(self, device="LFE5U-45F", toolchain="trellis", sys_clk_freq=int(50e6), sdram_module_cls="MT48LC16M16", **kwargs): platform = ulx3s.Platform(device=device, toolchain=toolchain) - # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + + # SoCCore ---------------------------------------------------------------------------------- + SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) @@ -65,10 +67,15 @@ class BaseSoC(SoCSDRAM): # SDR SDRAM -------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), cl=2) - sdram_module = getattr(litedram_modules, sdram_module_cls)(sys_clk_freq, "1:1") - self.register_sdram(self.sdrphy, - sdram_module.geom_settings, - sdram_module.timing_settings) + self.add_sdram("sdram", + phy = self.sdrphy, + module = getattr(litedram_modules, sdram_module_cls)(sys_clk_freq, "1:1"), + origin = self.mem_map["main_ram"], + size = kwargs.get("max_sdram_size", 0x40000000), + l2_cache_size = kwargs.get("l2_size", 8192), + l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), + l2_cache_reverse = True + ) # Build -------------------------------------------------------------------------------------------- diff --git a/litex/boards/targets/versa_ecp5.py b/litex/boards/targets/versa_ecp5.py index ce7a13d9..9edcd644 100755 --- a/litex/boards/targets/versa_ecp5.py +++ b/litex/boards/targets/versa_ecp5.py @@ -14,6 +14,7 @@ from litex.boards.platforms import versa_ecp5 from litex.build.lattice.trellis import trellis_args, trellis_argdict from litex.soc.cores.clock import * +from litex.soc.integration.soc_core import * from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * @@ -89,10 +90,15 @@ class BaseSoC(SoCSDRAM): self.add_csr("ddrphy") self.add_constant("ECP5DDRPHY", None) self.comb += self.crg.stop.eq(self.ddrphy.init.stop) - sdram_module = MT41K64M16(sys_clk_freq, "1:2") - self.register_sdram(self.ddrphy, - geom_settings = sdram_module.geom_settings, - timing_settings = sdram_module.timing_settings) + self.add_sdram("sdram", + phy = self.ddrphy, + module = MT41K64M16(sys_clk_freq, "1:2"), + origin = self.mem_map["main_ram"], + size = kwargs.get("max_sdram_size", 0x40000000), + l2_cache_size = kwargs.get("l2_size", 8192), + l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), + l2_cache_reverse = True + ) # EthernetSoC -------------------------------------------------------------------------------------- -- 2.30.2