From 4eae29801b823fde65df38576a90be0abb89e782 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Thu, 18 Jun 2020 11:18:30 +1000 Subject: [PATCH] uart: Rename sim_uart.vhdl to sim_pp_uart.vhdl Signed-off-by: Benjamin Herrenschmidt --- Makefile | 2 +- scripts/dependencies.py | 2 +- sim_uart.vhdl => sim_pp_uart.vhdl | 0 3 files changed, 2 insertions(+), 2 deletions(-) rename sim_uart.vhdl => sim_pp_uart.vhdl (100%) diff --git a/Makefile b/Makefile index 1e4b558..dcceff6 100644 --- a/Makefile +++ b/Makefile @@ -55,7 +55,7 @@ soc_files = $(core_files) wishbone_arbiter.vhdl wishbone_bram_wrapper.vhdl sync_ spi_rxtx.vhdl spi_flash_ctrl.vhdl -soc_sim_files = $(soc_files) sim_console.vhdl sim_uart.vhdl sim_bram_helpers.vhdl \ +soc_sim_files = $(soc_files) sim_console.vhdl sim_pp_uart.vhdl sim_bram_helpers.vhdl \ sim_bram.vhdl sim_jtag_socket.vhdl sim_jtag.vhdl dmi_dtm_xilinx.vhdl soc_sim_c_files = sim_vhpi_c.c sim_bram_helpers_c.c sim_console_c.c \ diff --git a/scripts/dependencies.py b/scripts/dependencies.py index 55c9181..63a20a4 100755 --- a/scripts/dependencies.py +++ b/scripts/dependencies.py @@ -39,7 +39,7 @@ sim_provides = { "dmi_dtm" : "dmi_dtm_xilinx.vhdl", "clock_generator" : "fpga/clk_gen_bypass.vhd", "main_bram" : "sim_bram.vhdl", - "pp_soc_uart" : "sim_uart.vhdl" + "pp_soc_uart" : "sim_pp_uart.vhdl" } if synth: diff --git a/sim_uart.vhdl b/sim_pp_uart.vhdl similarity index 100% rename from sim_uart.vhdl rename to sim_pp_uart.vhdl -- 2.30.2