From 4ebc0b502e988829702cfa12685b5e454f947f0f Mon Sep 17 00:00:00 2001 From: lkcl Date: Thu, 2 Jun 2022 16:59:47 +0100 Subject: [PATCH] --- openpower/sv/svp64_quirks.mdwn | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/openpower/sv/svp64_quirks.mdwn b/openpower/sv/svp64_quirks.mdwn index a333a4a51..b04d05a3d 100644 --- a/openpower/sv/svp64_quirks.mdwn +++ b/openpower/sv/svp64_quirks.mdwn @@ -120,6 +120,7 @@ widths as part of the actual operation, and the source and destination elwidth overrides, was particularly obtuse and hard to derive: some care and attention is advised, here, when reading the specification. + **Non-vectorised** The concept of a Vectorised halt (`attn`) makes no sense. There are never @@ -147,7 +148,10 @@ of a Scalar ISA and then adds additional instructions which only make sense in a Vector Context, such as Vector Shuffle, SVP64 goes to considerable lengths to keep strictly to augmentation and embedding of an entire Scalar ISA's instructions into an abstract Vectorisation -Context. +Context. That abstraction subdivides down into Categories appropriate +for the type of operation (Branch, CRs, Memory, Arithmetic), +and each Category has its own relevant but +ultimately rational quirks. # CR weird instructions -- 2.30.2