From 4ec30dd18846408159224c3684bed32e75b25c66 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 20 Jul 2022 20:20:06 +0100 Subject: [PATCH] rename substep to ssubstep, add dsubstep to SVP64State --- src/openpower/decoder/isa/caller.py | 64 ++++++++++++------------- src/openpower/decoder/isa/svstate.py | 18 +++++-- src/openpower/decoder/power_decoder2.py | 10 ++-- src/openpower/sv/svstate.py | 8 ++-- 4 files changed, 54 insertions(+), 46 deletions(-) diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py index 73fbecf3..6b89ea2c 100644 --- a/src/openpower/decoder/isa/caller.py +++ b/src/openpower/decoder/isa/caller.py @@ -1142,7 +1142,7 @@ class ISACaller(ISACallerHelper, ISAFPHelpers): in the class for later use. this to avoid problems with yield """ # go through all iterators in lock-step, advance to next remap_idx - srcstep, dststep, substep = self.get_src_dststeps() + srcstep, dststep, ssubstep = self.get_src_dststeps() # get four SVSHAPEs. here we are hard-coding SVSHAPE0 = self.spr['SVSHAPE0'] SVSHAPE1 = self.spr['SVSHAPE1'] @@ -1294,7 +1294,7 @@ class ISACaller(ISACallerHelper, ISAFPHelpers): self.update_nia() self.update_pc_next() return - srcstep, dststep, substep = self.get_src_dststeps() + srcstep, dststep, ssubstep = self.get_src_dststeps() pred_dst_zero = self.pred_dst_zero pred_src_zero = self.pred_src_zero vl = self.svstate.vl @@ -1472,11 +1472,11 @@ class ISACaller(ISACallerHelper, ISAFPHelpers): offsmul = yield self.dec2.in1_step log("D-field REMAP src", imm, offsmul) else: - offsmul = (srcstep * (subvl+1)) + substep + offsmul = (srcstep * (subvl+1)) + ssubstep log("D-field src", imm, offsmul) elif op == MicrOp.OP_STORE.value: # XXX NOTE! no bit-reversed STORE! this should not ever be used - offsmul = (dststep * (subvl+1)) + substep + offsmul = (dststep * (subvl+1)) + ssubstep log("D-field dst", imm, offsmul) # bit-reverse mode, rev already done through get_src_dst_steps() if ldstmode == SVP64LDSTmode.SHIFT.value: @@ -1651,13 +1651,13 @@ class ISACaller(ISACallerHelper, ISAFPHelpers): log("SVSTATE_NEXT: post-inc") # use actual src/dst-step here to check end, do NOT # use bit-reversed version - srcstep, dststep, substep = \ - self.new_srcstep, self.new_dststep, self.new_substep + srcstep, dststep, ssubstep = \ + self.new_srcstep, self.new_dststep, self.new_ssubstep remaps = self.get_remap_indices() remap_idxs = self.remap_idxs vl = self.svstate.vl subvl = yield self.dec2.rm_dec.rm_in.subvl - end_sub = substep == subvl + end_sub = ssubstep == subvl end_src = srcstep == vl-1 end_dst = dststep == vl-1 if self.allow_next_step_inc != 2: @@ -1728,13 +1728,13 @@ class ISACaller(ISACallerHelper, ISAFPHelpers): subvl = yield self.dec2.rm_dec.rm_in.subvl srcstep = self.svstate.srcstep dststep = self.svstate.dststep - substep = self.svstate.substep + ssubstep = self.svstate.ssubstep sv_a_nz = yield self.dec2.sv_a_nz fft_mode = yield self.dec2.use_svp64_fft in1 = yield self.dec2.e.read_reg1.data - log("SVP64: VL, subvl, srcstep, dststep, substep, sv_a_nz, " + log("SVP64: VL, subvl, srcstep, dststep, ssubstep, sv_a_nz, " "in1 fft, svp64", - vl, subvl, srcstep, dststep, substep, sv_a_nz, in1, fft_mode, + vl, subvl, srcstep, dststep, ssubstep, sv_a_nz, in1, fft_mode, self.is_svp64_mode) # get predicate mask (all 64 bits) @@ -1755,8 +1755,8 @@ class ISACaller(ISACallerHelper, ISAFPHelpers): srcmask = dstmask = get_predcr(self.crl, dstpred, vl) if sv_ptype == SVPtype.P2.value: srcmask = get_predcr(self.crl, srcpred, vl) - # work out if the substeps are completed - end_sub = substep == subvl + # work out if the ssubsteps are completed + end_sub = ssubstep == subvl log(" pmode", pmode) log(" reverse", reverse_gear) log(" ptype", sv_ptype) @@ -1781,10 +1781,10 @@ class ISACaller(ISACallerHelper, ISAFPHelpers): while (((1 << dststep) & dstmask) == 0) and (dststep != vl): log(" skip", bin(1 << dststep)) dststep += 1 - # and reset substep back to zero - substep = 0 + # and reset ssubstep back to zero + ssubstep = 0 else: - substep += 1 # advance substep + ssubstep += 1 # advance ssubstep # now work out if the relevant mask bits require zeroing if pred_dst_zero: @@ -1793,38 +1793,38 @@ class ISACaller(ISACallerHelper, ISAFPHelpers): pred_src_zero = ((1 << srcstep) & srcmask) == 0 # store new srcstep / dststep - self.new_srcstep, self.new_dststep, self.new_substep = \ - (srcstep, dststep, substep) + self.new_srcstep, self.new_dststep, self.new_ssubstep = \ + (srcstep, dststep, ssubstep) self.pred_dst_zero, self.pred_src_zero = pred_dst_zero, pred_src_zero log(" new srcstep", srcstep) log(" new dststep", dststep) - log(" new substep", substep) + log(" new ssubstep", ssubstep) def get_src_dststeps(self): - """gets srcstep, dststep, and substep + """gets srcstep, dststep, and ssubstep """ - return self.new_srcstep, self.new_dststep, self.new_substep + return self.new_srcstep, self.new_dststep, self.new_ssubstep def update_new_svstate_steps(self): # note, do not get the bit-reversed srcstep here! - srcstep, dststep, substep = \ - self.new_srcstep, self.new_dststep, self.new_substep + srcstep, dststep, ssubstep = \ + self.new_srcstep, self.new_dststep, self.new_ssubstep # update SVSTATE with new srcstep self.svstate.srcstep = srcstep self.svstate.dststep = dststep - self.svstate.substep = substep + self.svstate.ssubstep = ssubstep self.namespace['SVSTATE'] = self.svstate yield self.dec2.state.svstate.eq(self.svstate.value) yield Settle() # let decoder update srcstep = self.svstate.srcstep dststep = self.svstate.dststep - substep = self.svstate.substep + ssubstep = self.svstate.ssubstep vl = self.svstate.vl subvl = yield self.dec2.rm_dec.rm_in.subvl log(" srcstep", srcstep) log(" dststep", dststep) - log(" substep", substep) + log(" ssubstep", ssubstep) log(" vl", vl) log(" subvl", subvl) @@ -1848,7 +1848,7 @@ class ISACaller(ISACallerHelper, ISAFPHelpers): mvl = self.svstate.maxvl srcstep = self.svstate.srcstep dststep = self.svstate.dststep - substep = self.svstate.substep + ssubstep = self.svstate.ssubstep rm_mode = yield self.dec2.rm_dec.mode reverse_gear = yield self.dec2.rm_dec.reverse_gear sv_ptype = yield self.dec2.dec.op.SV_Ptype @@ -1859,7 +1859,7 @@ class ISACaller(ISACallerHelper, ISAFPHelpers): log(" rm.subvl", subvl) log(" svstate.srcstep", srcstep) log(" svstate.dststep", dststep) - log(" svstate.substep", substep) + log(" svstate.ssubstep", ssubstep) log(" mode", rm_mode) log(" reverse", reverse_gear) log(" out_vec", out_vec) @@ -1901,16 +1901,16 @@ class ISACaller(ISACallerHelper, ISAFPHelpers): def advance_svstate_steps(self, end_src=False, end_dst=False): subvl = yield self.dec2.rm_dec.rm_in.subvl - substep = self.svstate.substep - end_sub = substep == subvl + ssubstep = self.svstate.ssubstep + end_sub = ssubstep == subvl if end_sub: if not end_src: self.svstate.srcstep += SelectableInt(1, 7) if not end_dst: self.svstate.dststep += SelectableInt(1, 7) - self.svstate.substep = SelectableInt(0, 2) + self.svstate.ssubstep = SelectableInt(0, 2) else: - self.svstate.substep += SelectableInt(1, 2) # advance substep + self.svstate.ssubstep += SelectableInt(1, 2) # advance ssubstep def update_pc_next(self): # UPDATE program counter @@ -1923,7 +1923,7 @@ class ISACaller(ISACallerHelper, ISAFPHelpers): def svp64_reset_loop(self): self.svstate.srcstep = 0 self.svstate.dststep = 0 - self.svstate.substep = 0 + self.svstate.ssubstep = 0 log(" svstate.srcstep loop end (PC to update)") self.namespace['SVSTATE'] = self.svstate diff --git a/src/openpower/decoder/isa/svstate.py b/src/openpower/decoder/isa/svstate.py index 86b17f6b..9b8c89be 100644 --- a/src/openpower/decoder/isa/svstate.py +++ b/src/openpower/decoder/isa/svstate.py @@ -56,12 +56,20 @@ class SVP64State(SelectableInt): self.fsi['srcstep'].eq(value) @property - def substep(self): - return self.fsi['substep'].asint(msb0=True) + def dsubstep(self): + return self.fsi['dsubstep'].asint(msb0=True) - @substep.setter - def substep(self, value): - self.fsi['substep'].eq(value) + @dsubstep.setter + def dsubstep(self, value): + self.fsi['dsubstep'].eq(value) + + @property + def ssubstep(self): + return self.fsi['ssubstep'].asint(msb0=True) + + @ssubstep.setter + def ssubstep(self, value): + self.fsi['ssubstep'].eq(value) @property def subvl(self): diff --git a/src/openpower/decoder/power_decoder2.py b/src/openpower/decoder/power_decoder2.py index 15562783..52ae69ce 100644 --- a/src/openpower/decoder/power_decoder2.py +++ b/src/openpower/decoder/power_decoder2.py @@ -1306,15 +1306,15 @@ class PowerDecode2(PowerDecodeSubset): # get SVSTATE srcstep (TODO: elwidth etc.) needed below vl = Signal.like(self.state.svstate.vl) - subvl = Signal.like(self.state.svstate.subvl) + subvl = Signal.like(self.rm_dec.rm_in.subvl) srcstep = Signal.like(self.state.svstate.srcstep) dststep = Signal.like(self.state.svstate.dststep) - substep = Signal.like(self.state.svstate.substep) + ssubstep = Signal.like(self.state.svstate.ssubstep) comb += vl.eq(self.state.svstate.vl) comb += subvl.eq(self.rm_dec.rm_in.subvl) comb += srcstep.eq(self.state.svstate.srcstep) comb += dststep.eq(self.state.svstate.dststep) - comb += substep.eq(self.state.svstate.substep) + comb += ssubstep.eq(self.state.svstate.ssubstep) in1_step, in2_step = self.in1_step, self.in2_step in3_step = self.in3_step @@ -1357,9 +1357,9 @@ class PowerDecode2(PowerDecodeSubset): selectstep = dststep if out else srcstep step = Signal(7, name="step_%s" % rname.lower()) with m.If(self.remap_active[i]): - comb += step.eq((remapstep*(subvl+1))+substep) + comb += step.eq((remapstep*(subvl+1))+ssubstep) with m.Else(): - comb += step.eq((selectstep*(subvl+1))+substep) + comb += step.eq((selectstep*(subvl+1))+ssubstep) # reverse gear goes the opposite way with m.If(self.rm_dec.reverse_gear): comb += to_reg.data.eq(offs+svdec.reg_out+(vmax-1-step)) diff --git a/src/openpower/sv/svstate.py b/src/openpower/sv/svstate.py index da1b5fac..46445845 100644 --- a/src/openpower/sv/svstate.py +++ b/src/openpower/sv/svstate.py @@ -11,8 +11,8 @@ https://libre-soc.org/openpower/sv/sprs/ | 7:13 | vl | Vector Length | | 14:20 | srcstep | for srcstep = 0..VL-1 | | 21:27 | dststep | for dststep = 0..VL-1 | -| 28:29 | subvl | Sub-vector length | -| 30:31 | substep | for substep = 0..SUBVL-1 | +| 28:29 | dsubstep | for dsubstep = 0..SUBVL-1 | +| 30:31 | ssubstep | for ssubstep = 0..SUBVL-1 | | 32:33 | mi0 | REMAP RA SVSHAPE0-3 | | 34:35 | mi1 | REMAP RB SVSHAPE0-3 | | 36:37 | mi2 | REMAP RC SVSHAPE0-3 | @@ -39,8 +39,8 @@ class SVSTATERec(Record): ("mi2", 2), ("mi1", 2), ("mi0", 2), - ("substep", 2), - ("subvl", 2), + ("ssubstep", 2), + ("dsunstep", 2), ("dststep", 7), ("srcstep", 7), ("vl", 7), -- 2.30.2